Abstract: A partial discharge detection apparatus for detecting partial discharge in a power cable and recognizing an insulation deterioration state of the power cable. A low-speed AD converter converts an analog signal of an AC waveform flowing through a power cable into a digital signal. A high-speed AD converter converts an analog signal of a partial discharge current into a digital signal. The partial discharge is detected based on the maximum value or the sum of a current value obtained from the digital signal of the partial discharge current obtained by the conversion of the high-speed AD converter, for each phase of the AC waveform, which is obtained from the digital signal of the AC waveform flowing in the power cable. The digital signal is obtained by the conversion of the low-speed AD converter.

Abstract: In the related art, since there is a difference in communication delay time in a round-trip communication path due to packet clogging in a network configuration using a network relay device, there is a problem that time cannot be synchronized. In order to solve the above problem, in the present invention, a time synchronization unit 131 is controlled by the time synchronization control unit 130 to perform time synchronization once, delays of an egress path and an ingress path of the time packet on the basis of the synchronization time are calculated, and time synchronization processing is executed using a time of the time packet in a case where the calculated values are equal to each other.

Abstract: A partial discharge detection apparatus includes low-speed and high-speed AD converters. The low-speed AD converter converts an analog signal of an AC waveform flowing through a power cable into a digital signal. The high-speed AD converter converts an analog signal of a partial discharge current into a digital signal. The analog signal is in a plurality of Nyquist frequency domains defined for each of two different types of sampling frequencies. The partial discharge is detected by a partial-discharge-detection digital signal processing unit based on the maximum value or the sum of a current value obtained from the digital signal of the partial discharge current obtained by the conversion of the high-speed AD converter, for each phase of the AC waveform, which is obtained from the digital signal of the AC waveform flowing in the power cable. The digital signal is obtained by the conversion of the low-speed AD converter.

Abstract: There is provided a communication control device including: a real-time communication status extraction unit that acquires a communication timing of real-time data; a dynamic fragment size determination unit that acquires a fragment size of sending data which can be sent until the communication timing acquired by the real-time communication status extraction unit; a fragment processing unit that fragments non-real-time data to have at least a fragment size which is equal to or less than the fragment size acquired by the dynamic fragment size determination unit; and a communication unit that sends the non-real-time data, which is fragmented by the fragment processing unit, before the communication timing of the real-time data.

Abstract: There is provided a communication control device including: a real-time communication status extraction unit that acquires a communication timing of real-time data; a dynamic fragment size determination unit that acquires a fragment size of sending data which can be sent until the communication timing acquired by the real-time communication status extraction unit; a fragment processing unit that fragments non-real-time data to have at least a fragment size which is equal to or less than the fragment size acquired by the dynamic fragment size determination unit; and a communication unit that sends the non-real-time data, which is fragmented by the fragment processing unit, before the communication timing of the real-time data.

Abstract: Disclosed are a digital protection control system and a digital protection control apparatus, wherein the digital protection control apparatus can easily be made to have more terminals, even when the number of terminals of a power transmission line increases. The digital protection control system has, as terminal stations thereof, a reference station that is to become the reference point for the sampling time at which power grid current information is to be taken in, tail-end stations that take in power grid current information from the power grid system, and intermediate stations that are connected between the reference station and the tail-end stations via transmission paths. The intermediate station is provided with an uplink transmission unit that is connected to a transmission path at the reference station side thereof, and a plurality of downlink transmission units that are connected to transmission paths at the tail-end station side thereof.

Abstract: Disclosed are a digital protection control system and a digital protection control apparatus, wherein the digital protection control apparatus can easily be made to have more terminals, even when the number of terminals of a power transmission line increases. The digital protection control system has, as terminal stations thereof, a reference station that is to become the reference point for the sampling time at which power grid current information is to be taken in, tail-end stations that take in power grid current information from the power grid system, and intermediate stations that are connected between the reference station and the tail-end stations via transmission paths. The intermediate station is provided with an uplink transmission unit that is connected to a transmission path at the reference station side thereof, and a plurality of downlink transmission units that are connected to transmission paths at the tail-end station side thereof.

Abstract: A device for controlling the table capacity smaller comprises a table of logarithms and a table of exponents preserving values of a logarithmic function and exponential function with a base of the second power, a multiplier, a shift unit for shifting the input value by a proper integer when the domain of logarithm is not included in the input value range of the table of logarithms, a logarithm addition unit for adding the shift amount to the value referred to in the table of logarithms, an exponent subtraction unit for subtracting a proper integer L from the input value when the domain of the exponential function is not included in the input value range of the table of exponents, and an exponent shift unit for shifting the referred value in the table of exponents the subtraction amount. A high-speed processing unit comprises a converter for converting floating-point data to fixed-point data having a bit of decimal point.

Abstract: A graphics processor comprises: a light source table holding light source data; a conversion unit for converting the light source data to be set in the light source table from a float type (single-precision floating point real number type) into an int type (integer type); an inner product calculation unit for calculating the inner products of normal directions, light source directions and sight line directions at the vertices based on the light source data; and a color calculation unit for performing light source computations based on the calculated inner products to determine the colors of the vertices.

Abstract: A device for controlling the table capacity smaller comprises a table of logarithms and a table of exponents preserving values of a logarithmic function and exponential function with a base of the second power, a multiplier, a shift unit for shifting the input value by a proper integer when the domain of logarithm is not included in the input value range of the table of logarithms, a logarithm addition unit for adding the shift amount to the value referred to in the table of logarithms, an exponent subtraction unit for subtracting a proper integer L from the input value when the domain of the exponential function is not included in the input value range of the table of exponents, and an exponent shift unit for shifting the referred value in the table of exponents the subtraction amount. A high-speed processing unit comprises a converter for converting floating-point data to fixed-point data having a bit of decimal point.

Abstract: A graphics processor comprises: a light source table holding light source data; a conversion unit for converting the light source data to be set in the light source table from a float type (single-precision floating point real number type) into an int type (integer type); an inner product calculation unit for calculating the inner products of normal directions, light source directions and sight line directions at the vertices based on the light source data; and a color calculation unit for performing light source computations based on the calculated inner products to determine the colors of the vertices.

Abstract: The hardware of an over-sampling A/D and D/A converter is provided, which hardware is capable of being operated with either kind of software: one corresponding to a first method in which the over-sampling ratio is fixed and the other corresponding to a second method in which the over-sampling ratio is variable. The value N3 written on the pseudo-frequency-dividing-ratio-register 11 and the value N4 written on the pseudo-over-sampling-ratio-register 21 are converted through a user interface into the frequency dividing ratio N1 by the conversion circuit 12 and the converted result is written in the frequency-dividing-ratio-register 10.

Abstract: In order to reduce the consumption of power of an isolator interface and an ADC, it is proposed to operate a calling signal reception or Caller ID signal reception function only with power supplied from the system switch while maintaining the on-hook condition of a telephone. At the time of normal operation, the output of the analogue digital converter is input to an isolator through the isolator interface, and at the time of the calling signal reception or the caller identification information reception, the output of the analogue digital converter is input directly to the isolator.

Abstract: A graphics processor comprises: a light source table holding light source data; a conversion unit for converting the light source data to be set in the light source table from a float type (single-precision floating point real number type) into an int type (integer type); an inner product calculation unit for calculating the inner products of normal directions, light source directions and sight line directions at the vertices based on the light source data; and a color calculation unit for performing light source computations based on the calculated inner products to determine the colors of the vertices.

Abstract: A device for controlling the table capacity smaller comprises a table of logarithms and a table of exponents preserving values of a logarithmic function and exponential function with a base of the second power, a multiplier, a shift unit for shifting the input value by a proper integer when the domain of logarithm is not included in the input value range of the table of logarithms, a logarithm addition unit for adding the shift amount to the value referred to in the table of logarithms, an exponent subtraction unit for subtracting a proper integer L from the input value when the domain of the exponential function is not included in the input value range of the table of exponents, and an exponent shift unit for shifting the referred value in the table of exponents the subtraction amount. A high-speed processing unit comprises a converter for converting floating-point data to fixed-point data having a bit of decimal point.

Abstract: A graphics display system includes a host processor calculating graphic data and providing the graphic data to a graphics processor, and frame memories which store the graphic pixel data and supply display data to display devices. The graphics display system also includes a first register group which stores the graphics data, a second register group which converts and/or stores the data in the first register group, a pixel generator which generates pixels according to the graphic data in the second register group, and a plotter which writes the pixel data generated in the pixel generator in the frame memories. The second register group fetches the data from the first register group when the host processor issues a command for plotting, holds the data previously written by the host processor. At the same time, when the host processor issues a command for plotting, the specified graphic type is written in the graphic processor as well as data calculated based on the first and second register groups.

Abstract: A graphics display system includes a host processor calculating graphic data and providing the graphic data to a graphics processor, and frame memories which store the graphic pixel data and supply display data to display devices. The graphics display system also includes a first register group which stores the graphics data, a second register group which converts and/or stores the data in the first register group, a pixel generator which generates pixels according to the graphic data in the second register group, and a plotter which writes the pixel data generated in the pixel generator in the frame memories. The second register group fetches the data from the first register group when the host processor issues a command for plotting, holds the data previously written by the host processor. At the same time, when the host processor issues a command for plotting, the specified graphic type is written in the graphic processor as sell as data calculated based on the first and second register groups.