Patents by Inventor Kazuhisa Tsunoi

Kazuhisa Tsunoi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110220405
    Abstract: A method for manufacturing a multilayer printed wiring board, the method includes forming a group of first through holes in a first insulating substrate; forming a group of second through holes in a second insulating substrate that has the same shape and the same size as a shape and a size, respectively, of the first insulating substrate, the second through holes having the same shape and the same size as a shape and a size, respectively, of the first through holes and being formed at the same positions as positions at which the first through holes are formed. At least one of the first through holes is filled with a first conductive member and at least one of the second through holes is filled with a second conductive member. And stacking the first insulating substrate and the second insulating substrate together.
    Type: Application
    Filed: December 6, 2010
    Publication date: September 15, 2011
    Applicant: FUJITSU LIMITED
    Inventor: Kazuhisa TSUNOI
  • Publication number: 20100200643
    Abstract: A method for producing an electronic part unit, the method includes: mounting a first electronic part on a first surface of a first substrate by reflow soldering; mounting a second electronic part on a second surface of a second substrate by reflow soldering; adhering a second surface of the first substrate to a first surface of a third substrate; and adhering a second surface of the second substrate to a second surface of the third substrate.
    Type: Application
    Filed: January 29, 2010
    Publication date: August 12, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Nobuo Taketomi, Shigeo Iriguchi, Kazuhisa Tsunoi, Kiyoyuki Hatanaka
  • Patent number: 6787925
    Abstract: A method of mounting a semiconductor device having bumps on a board having pads so that each of the bumps is joined to a corresponding one of the pads is provided. Adhesive to be hardened by heat is provided between the semiconductor device and the board. The method includes the steps of pressing the bumps of the semiconductor device on the pads of the board, and heating a portion in which each of the bumps and a corresponding one of the pads are in contact with each other. A pressure of the bumps to the pads reaches a predetermined value before a temperature of the adhesive to which heat is supplied in the above step reaches a temperature at which the adhesive is hardened.
    Type: Grant
    Filed: March 14, 2001
    Date of Patent: September 7, 2004
    Assignee: Fujitsu Limited
    Inventors: Kazuhisa Tsunoi, Hidehiko Kira, Shunji Baba, Akira Fujii, Toshihiro Kusagaya, Kenji Kobae, Norio Kainuma, Naoki Ishikawa, Satoshi Emoto
  • Patent number: 6482676
    Abstract: A method of mounting a semiconductor chip part on a substrate, which is capable of realizing high efficiency and high reliability of the mounting works. A leading end of a conductive wire is contact-bonded onto each pad of a semiconductor chip part, followed by tearing of the wire, to form a two-step bump having an upper step portion and a lower step portion larger in volume than the upper step portion. Only the upper step portions of the bumps are then brought in press-contact with a single flattening tool member having a flat surface in such a manner that heights of all of the bumps are made nearly equal to each other. A conductive paste is stuck on the bumps, and the substrate is coated with an adhesive. Thus, the semiconductor chip part is heated and pressurized onto the substrate by a mounting tool in such a state in which the pads are aligned with the corresponding lands of the substrate, to plastically deform the whole of the upper step portions and the lower step portions of the bumps.
    Type: Grant
    Filed: July 1, 1997
    Date of Patent: November 19, 2002
    Assignee: Fujitsu Limited
    Inventors: Kazuhisa Tsunoi, Akira Fujii, Shunji Baba, Yoshikazu Hirano
  • Patent number: 6458237
    Abstract: A method of mounting a semiconductor device having bumps on a board having pads so that each of the bumps is joined to a corresponding one of the pads is provided. Adhesive to be hardened by heat is provided between the semiconductor device and the board. The method includes the steps of pressing the bumps of the semiconductor device on the pads of the board, and heating a portion in which each of the bumps and a corresponding one of the pads are in contact with each other. A pressure of the bumps to the pads reaches a predetermined value before a temperature of the adhesive to which heat is supplied in the above step reaches a temperature at which the adhesive is hardened.
    Type: Grant
    Filed: March 20, 1998
    Date of Patent: October 1, 2002
    Assignee: Fujitsu Limited
    Inventors: Kazuhisa Tsunoi, Hidehiko Kira, Shunji Baba, Akira Fujii, Toshihiro Kusagaya, Kenji Kobae, Norio Kainuma, Naoki Ishikawa, Satoshi Emoto
  • Patent number: 6429516
    Abstract: A bare chip mounting structure includes a bare chip having inlet or outlet terminals, an interposer having openings at positions corresponding to said inlet or outlet terminals of the bare chip and a circuit board having conductive pads wherein the bare chip is mounted on the circuit board by means of the interposer in such a manner that the inlet or outlet terminals are electrically connected to the conductive pads of the circuit board through the openings of the interposer.
    Type: Grant
    Filed: November 10, 1997
    Date of Patent: August 6, 2002
    Assignee: Fujitsu, Limited
    Inventor: Kazuhisa Tsunoi
  • Publication number: 20020048847
    Abstract: A method of mounting a semiconductor chip part on a substrate, which is capable of realizing high efficiency and high reliability of the mounting works. A leading end of a conductive wire is contact-bonded onto each pad of a semiconductor chip part, followed by tearing of the wire, to form a two-step bump having an upper step portion and a lower step portion larger in volume than the upper step portion. Only the upper step portions of the bumps are then brought in press-contact with a single flattening tool member having a flat surface in such a manner that heights of all of the bumps are made nearly equal to each other. A conductive paste is stuck on the bumps, and the substrate is coated with an adhesive. Thus, the semiconductor chip part is heated and pressurized onto the substrate by a mounting tool in such a state in which the pads are aligned with the corresponding lands of the substrate, to plastically deform the whole of the upper step portions and the lower step portions of the bumps.
    Type: Application
    Filed: July 1, 1997
    Publication date: April 25, 2002
    Inventors: KAZUHISA TSUNOI, AKIRA FUJII, SHUNJI BABA, YOSHIKAZU HIRANO
  • Publication number: 20020045293
    Abstract: A bare chip mounting structure includes a bare chip having inlet or outlet terminals, an interposer having openings at positions corresponding to said inlet or outlet terminals of the bare chip and a circuit board having conductive pads wherein the bare chip is mounted on the circuit board by means of the interposer in such a manner that the inlet or outlet terminals are electrically connected to the conductive pads of the circuit board through the openings of the interposer.
    Type: Application
    Filed: November 10, 1997
    Publication date: April 18, 2002
    Applicant: FUJITSU LIMITED
    Inventor: KAZUHISA TSUNOI
  • Patent number: 6291269
    Abstract: A semiconductor bare chip includes a plurality of stud bumps provided on the surface of the semiconductor bare chip body, each of the stud bumps including a seat and a head protruding from the seat. A height of the head is less than a thickness of electrodes on said board.
    Type: Grant
    Filed: October 1, 1999
    Date of Patent: September 18, 2001
    Assignee: Fujitsu Limited
    Inventors: Hidehiko Kira, Kiyoshi Fukui, Kazuhisa Tsunoi, Shunji Baba
  • Publication number: 20010011774
    Abstract: A method of mounting a semiconductor device having bumps on a board having pads so that each of the bumps is joined to a corresponding one of the pads is provided. Adhesive to be hardened by heat is provided between the semiconductor device and the board. The method includes the steps of pressing the bumps of the semiconductor device on the pads of the board, and heating a portion in which each of the bumps and a corresponding one of the pads are in contact with each other. A pressure of the bumps to the pads reaches a predetermined value before a temperature of the adhesive to which heat is supplied in the above step reaches a temperature at which the adhesive is hardened.
    Type: Application
    Filed: March 14, 2001
    Publication date: August 9, 2001
    Applicant: Fujitsu Limited
    Inventors: Kazuhisa Tsunoi, Hidehiko Kira, Shunji Baba, Akira Fujii, Toshihiro Kusagaya, Kenji Kobae, Norio Kainuma, Naoki Ishikawa, Satoshi Emoto
  • Patent number: 6177730
    Abstract: A semiconductor bare chip includes a plurality of stud bumps provided on the surface of the semiconductor bare chip body, each of the stud bumps including a seat and a head protruding from the seat. A height of the head is less than a thickness of electrodes on said board.
    Type: Grant
    Filed: February 10, 1998
    Date of Patent: January 23, 2001
    Assignee: Fujitsu Limited
    Inventors: Hidehiko Kira, Kiyoshi Fukui, Kazuhisa Tsunoi, Shunji Baba
  • Patent number: 4675789
    Abstract: A high density multilayer printed circuit board comprising generally parallel signal layers, electric source layers, and ground layers, with insulating layers arranged between the signal layers and the electric source layers, between the electric source layers and the ground layers, and between the ground layers and the signal layers respectively. Conductor portions are formed in through holes which are opened in a direction transverse to the signal layers, electric source layers, and ground layers. The conductor portions are electrically connected to the signal layers and/or the electric source layers, and/or the ground layers, through the lands thereof, the connections of the lands being substantially equally distributed among the conductor portions.
    Type: Grant
    Filed: December 20, 1985
    Date of Patent: June 23, 1987
    Assignee: Fujitsu Limited
    Inventors: Kiyoshi Kuwabara, Mikio Nishihara, Kazuhisa Tsunoi