Patents by Inventor Kazuhisa Ukai
Kazuhisa Ukai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240120017Abstract: Provided is a RAM including a first read bit line, a first write bit line, a second read bit line, a second write bit line, a charge circuit configured to charge one of the first and second read bit lines and the first and second write bit lines at a time of short-circuit detection, and a discharge circuit configured to discharge the other of the first and second read bit lines and the first and second write bit lines at the time of the short-circuit detection.Type: ApplicationFiled: September 26, 2023Publication date: April 11, 2024Inventors: Kosuke Ijigawa, Kazuhisa Ukai
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Patent number: 11923017Abstract: A non-volatile storage device includes a memory that stores data in a non-volatile manner, a power supply that generates an internal voltage to feed it to the memory, a controller that controls the memory and the power supply, an A/D converter that performs A/D conversion on the internal voltage, and a fault detector that detects a fault related to data written in the memory based on the output of the A/D converter.Type: GrantFiled: June 15, 2020Date of Patent: March 5, 2024Assignee: Rohm Co., Ltd.Inventors: Kazuhisa Ukai, Koji Nigoriike
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Publication number: 20220246223Abstract: A non-volatile storage device includes a memory that stores data in a non-volatile manner, a power supply that generates an internal voltage to feed it to the memory, a controller that controls the memory and the power supply, an A/D converter that performs A/D conversion on the internal voltage, and a fault detector that detects a fault related to data written in the memory based on the output of the A/D converter.Type: ApplicationFiled: June 15, 2020Publication date: August 4, 2022Inventors: Kazuhisa Ukai, Koji Nigoriike
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Patent number: 10818355Abstract: Disclosed is a semiconductor memory device including a memory cell based on a static random access memory having a 6T or 4T2R configuration and including a first internal node, a second internal node, a first ferroelectric capacitor, and a second ferroelectric capacitor, the first ferroelectric capacitor and the second ferroelectric capacitor having respective first ends connected respectively to the first internal node and the second internal node. For recovering data stored in a non-volatile fashion in the first ferroelectric capacitor and the second ferroelectric capacitor, a first access transistor connected between the first internal node and a first bit line and a second access transistor connected between the second internal node and a second bit line are turned on, and respective capacitive components of the first bit line and the second bit line are used as load capacitances.Type: GrantFiled: April 30, 2019Date of Patent: October 27, 2020Assignee: ROHM CO., LTD.Inventors: Takaaki Fuchikami, Kazutaka Miyamoto, Hiromitsu Kimura, Kazuhisa Ukai
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Patent number: 10700076Abstract: A nonvolatile semiconductor storage device includes a plurality of cell transistor pairs including a pair of cell transistors sharing a first node connected to a bit line or a source line, and a dummy gate line laid in parallel with gate lines of the cell transistors, the dummy gate line applying an off voltage to a dummy transistor between the cell transistor pairs. The gate lines and the dummy gate line may be laid at equal intervals. A plurality of impurity diffusion layers corresponding to the first node and second nodes of the cell transistors may be formed at equal intervals in a continuous active region.Type: GrantFiled: November 1, 2018Date of Patent: June 30, 2020Assignee: ROHM CO., LTD.Inventors: Kazuhisa Ukai, Koji Nigoriike
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Publication number: 20190341109Abstract: Disclosed is a semiconductor memory device including a memory cell based on a static random access memory having a 6T or 4T2R configuration and including a first internal node, a second internal node, a first ferroelectric capacitor, and a second ferroelectric capacitor, the first ferroelectric capacitor and the second ferroelectric capacitor having respective first ends connected respectively to the first internal node and the second internal node. For recovering data stored in a non-volatile fashion in the first ferroelectric capacitor and the second ferroelectric capacitor, a first access transistor connected between the first internal node and a first bit line and a second access transistor connected between the second internal node and a second bit line are turned on, and respective capacitive components of the first bit line and the second bit line are used as load capacitances.Type: ApplicationFiled: April 30, 2019Publication date: November 7, 2019Inventors: TAKAAKI FUCHIKAMI, KAZUTAKA MIYAMOTO, HIROMITSU KIMURA, KAZUHISA UKAI
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Patent number: 10381082Abstract: A nonvolatile semiconductor storage device has floating-gate memory cells and a memory control circuit which controls them. During programming operation of the memory cells, the memory control circuit makes the potentials at the backgate and source of the memory cells equal. For example, during programming operation of the memory cells, the memory control circuit short-circuits together the backgate and source of the memory cells. For another example, during programming operation of the memory cells, the memory control circuit switches from a state where the potentials at the backgate and source of the memory cells are equal to a floating state.Type: GrantFiled: April 30, 2018Date of Patent: August 13, 2019Assignee: Rohm Co., Ltd.Inventors: Tsuyoshi Okamoto, Kazuhisa Ukai, Seiichi Yamamoto
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Publication number: 20190131311Abstract: A nonvolatile semiconductor storage device includes a plurality of cell transistor pairs including a pair of cell transistors sharing a first node connected to a bit line or a source line, and a dummy gate line laid in parallel with gate lines of the cell transistors, the dummy gate line applying an off voltage to a dummy transistor between the cell transistor pairs. The gate lines and the dummy gate line may be laid at equal intervals. A plurality of impurity diffusion layers corresponding to the first node and second nodes of the cell transistors may be formed at equal intervals in a continuous active region.Type: ApplicationFiled: November 1, 2018Publication date: May 2, 2019Inventors: KAZUHISA UKAI, KOJI NIGORIIKE
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Publication number: 20180315480Abstract: A nonvolatile semiconductor storage device has floating-gate memory cells and a memory control circuit which controls them. During programming operation of the memory cells, the memory control circuit makes the potentials at the backgate and source of the memory cells equal. For example, during programming operation of the memory cells, the memory control circuit short-circuits together the backgate and source of the memory cells. For another example, during programming operation of the memory cells, the memory control circuit switches from a state where the potentials at the backgate and source of the memory cells are equal to a floating state.Type: ApplicationFiled: April 30, 2018Publication date: November 1, 2018Inventors: Tsuyoshi OKAMOTO, Kazuhisa Ukai, Seiichi Yamamoto
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Patent number: 9741397Abstract: A semiconductor memory device includes a memory array including a plurality of element blocks, the plurality of element blocks including end-portion element blocks arranged at an end portion of the memory array, and at least one dummy block disposed adjacent to the end-portion element blocks, the at least one dummy block being not in practical use. A layout pattern of the at least one dummy block is configured to correspond to only a portion of a layout pattern of the plurality of element blocks.Type: GrantFiled: February 26, 2015Date of Patent: August 22, 2017Assignee: Rohm Co., Ltd.Inventor: Kazuhisa Ukai
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Publication number: 20150170713Abstract: A semiconductor memory device includes a memory array including a plurality of element blocks, the plurality of element blocks including end-portion element blocks arranged at an end portion of the memory array, and at least one dummy block disposed adjacent to the end-portion element blocks, the at least one dummy block being not in practical use. A layout pattern of the at least one dummy block is configured to correspond to only a portion of a layout pattern of the plurality of element blocks.Type: ApplicationFiled: February 26, 2015Publication date: June 18, 2015Inventor: Kazuhisa Ukai
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Patent number: 9001562Abstract: A semiconductor memory device includes a memory array including a plurality of element blocks; the plurality of element blocks including end-portion element blocks arranged at an end portion of the memory array, and at least one dummy block disposed adjacent to the end-portion element blocks, the at least one dummy block being not in practical use. A layout pattern of the at least one dummy block is configured to correspond to only a portion of a layout pattern of the plurality of element blocks.Type: GrantFiled: February 8, 2012Date of Patent: April 7, 2015Assignee: Rohm Co., Ltd.Inventor: Kazuhisa Ukai
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Publication number: 20120201071Abstract: A semiconductor memory device includes a memory array including a plurality of element blocks; the plurality of element blocks including end-portion element blocks arranged at an end portion of the memory array, and at least one dummy block disposed adjacent to the end-portion element blocks, the at least one dummy block being not in practical use. A layout pattern of the at least one dummy block is configured to correspond to only a portion of a layout pattern of the plurality of element blocks.Type: ApplicationFiled: February 8, 2012Publication date: August 9, 2012Applicant: ROHM CO., LTD.Inventor: Kazuhisa Ukai