Patents by Inventor Kazuhito Ichinose

Kazuhito Ichinose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180261467
    Abstract: It is possible to prevent deterioration of a redistribution layer due to exposure of the redistribution layer from an upper insulating film and the resultant reaction with moisture, ions, or the like. As means thereof, in a semiconductor device having a plurality of wiring layers formed in an element formation region and having a redistribution layer connected with a pad electrode which is an uppermost wiring layer, a dummy pattern is arranged in a region closer to a scribe region than the redistribution layer.
    Type: Application
    Filed: October 1, 2015
    Publication date: September 13, 2018
    Inventors: Masahiro MATSUMOTO, Kazuhito ICHINOSE, Akira YAJIMA
  • Patent number: 9984973
    Abstract: Pretreatment is carried out in a first chamber. Then, a mixed gas of titanium tetrachloride and hydrogen is supplied into a second chamber. At this time, conditions are set such that partial pressure of the titanium tetrachloride is higher than 3 Pa. The conditions are set such that the product of the partial pressure of the titanium tetrachloride and supply time is greater than 800 Pa·second. The titanium tetrachloride continues to be supplied into the second chamber to form a titanium film under prescribed temperature conditions in a plasma atmosphere. The temperature conditions are set such that temperature is higher than temperature at which titanium silicide is formed and lower than temperature at which a metal silicide film agglomerates. A titanium nitride film is formed in a third chamber.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: May 29, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Kazuhito Ichinose
  • Publication number: 20170330833
    Abstract: Pretreatment is carried out in a first chamber. Then, a mixed gas of titanium tetrachloride and hydrogen is supplied into a second chamber. At this time, conditions are set such that partial pressure of the titanium tetrachloride is higher than 3 Pa. The conditions are set such that the product of the partial pressure of the titanium tetrachloride and supply time is greater than 800 Pa·second. The titanium tetrachloride continues to be supplied into the second chamber to form a titanium film under prescribed temperature conditions in a plasma atmosphere. The temperature conditions are set such that temperature is higher than temperature at which titanium silicide is formed and lower than temperature at which a metal silicide film agglomerates. A titanium nitride film is formed in a third chamber.
    Type: Application
    Filed: August 2, 2017
    Publication date: November 16, 2017
    Applicant: Renesas Electronics Corporation
    Inventor: Kazuhito ICHINOSE
  • Patent number: 9754884
    Abstract: Pretreatment is carried out in a first chamber. Then, a mixed gas of titanium tetrachloride and hydrogen is supplied into a second chamber. At this time, conditions are set such that partial pressure of the titanium tetrachloride is higher than 3 Pa. The conditions are set such that the product of the partial pressure of the titanium tetrachloride and supply time is greater than 800 Pa·second. The titanium tetrachloride continues to be supplied into the second chamber to form a titanium film under prescribed temperature conditions in a plasma atmosphere. The temperature conditions are set such that temperature is higher than temperature at which titanium silicide is formed and lower than temperature at which a metal silicide film agglomerates. A titanium nitride film is formed in a third chamber.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: September 5, 2017
    Assignee: Renesas Electronics Corporation
    Inventor: Kazuhito Ichinose
  • Publication number: 20170018502
    Abstract: Pretreatment is carried out in a first chamber. Then, a mixed gas of titanium tetrachloride and hydrogen is supplied into a second chamber. At this time, conditions are set such that partial pressure of the titanium tetrachloride is higher than 3 Pa. The conditions are set such that the product of the partial pressure of the titanium tetrachloride and supply time is greater than 800 Pa·second. The titanium tetrachloride continues to be supplied into the second chamber to form a titanium film under prescribed temperature conditions in a plasma atmosphere. The temperature conditions are set such that temperature is higher than temperature at which titanium silicide is formed and lower than temperature at which a metal silicide film agglomerates. A titanium nitride film is formed in a third chamber.
    Type: Application
    Filed: July 12, 2016
    Publication date: January 19, 2017
    Applicant: Renesas Electronics Corporation
    Inventor: Kazuhito ICHINOSE
  • Publication number: 20160079188
    Abstract: Disclosed is a semiconductor device whose reliability can be improved. The semiconductor device includes: first wiring formed over a semiconductor substrate via a first insulating film; a second insulating film that includes an inorganic film covering the first wiring and that has a flat surface on which CMP processing has been performed; a third insulating film that is formed over the second insulating film and includes an inorganic film having moisture resistance higher than that of the second insulating film; and second wiring formed over the third insulating film. The thickness of the second wiring is 10 times or more larger than that of the first wiring, and the second wiring is located over the third insulating film without an organic insulating film being interposed between itself and the third insulating film.
    Type: Application
    Filed: November 25, 2015
    Publication date: March 17, 2016
    Inventors: Kazuhito ICHINOSE, Seiji MURANAKA, Kazuyuki OMORI
  • Patent number: 9230909
    Abstract: Disclosed is a semiconductor device whose reliability can be improved. The semiconductor device includes: first wiring formed over a semiconductor substrate via a first insulating film; a second insulating film that includes an inorganic film covering the first wiring and that has a flat surface on which CMP processing has been performed; a third insulating film that is formed over the second insulating film and includes an inorganic film having moisture resistance higher than that of the second insulating film; and second wiring formed over the third insulating film. The thickness of the second wiring is 10 times or more larger than that of the first wiring, and the second wiring is located over the third insulating film without an organic insulating film being interposed between itself and the third insulating film.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: January 5, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuhito Ichinose, Seiji Muranaka, Kazuyuki Omori
  • Publication number: 20150035156
    Abstract: Disclosed is a semiconductor device whose reliability can be improved. The semiconductor device includes: first wiring formed over a semiconductor substrate via a first insulating film; a second insulating film that includes an inorganic film covering the first wiring and that has a flat surface on which CMP processing has been performed; a third insulating film that is formed over the second insulating film and includes an inorganic film having moisture resistance higher than that of the second insulating film; and second wiring formed over the third insulating film. The thickness of the second wiring is 10 times or more larger than that of the first wiring, and the second wiring is located over the third insulating film without an organic insulating film being interposed between itself and the third insulating film.
    Type: Application
    Filed: July 29, 2014
    Publication date: February 5, 2015
    Inventors: Kazuhito Ichinose, Seiji Muranaka, Kazuyuki Omori
  • Patent number: 8685854
    Abstract: A process for burying a tungsten member into a blind hole formed in a wafer, in which blind hole a through via is to be made. Film-formation (for forming the tungsten member) is carried out to position, at the periphery of the wafer, the outer circumference of the tungsten member inside the outer circumference of a barrier metal beneath the tungsten film. This process makes it possible to bury the tungsten member, which may be relatively thin, into the blind hole, which may be relatively large, so as to decrease a warp of the wafer and further prevent an underlying layer beneath the tungsten member from being peeled at the periphery of the wafer.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: April 1, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuhito Ichinose, Kotaro Kihara, Tatsunori Murata
  • Patent number: 8344511
    Abstract: To provide a semiconductor device which can reduce an electrical resistance between a plug and a silicide region, and a manufacturing method thereof. At least one semiconductor element having a silicide region, is formed over a semiconductor substrate. An interlayer insulating film is formed over the silicide region. A through hole having an inner surface including a bottom surface comprised of the silicide regions is formed in the interlayer insulating film. A Ti (titanium) film covering the inner surface of the hole is formed by a chemical vapor deposition method. At least a surface of the Ti film is nitrided so as to forma barrier metal film covering the inner surface. A plug is formed to fill the through hole via the barrier metal film.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: January 1, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuhito Ichinose, Yukari Imai
  • Publication number: 20120161244
    Abstract: To provide a semiconductor device which can reduce an electrical resistance between a plug and a silicide region, and a manufacturing method thereof. At least one semiconductor element having a silicide region, is formed over a semiconductor substrate. An interlayer insulating film is formed over the silicide region. A through hole having an inner surface including a bottom surface comprised of the silicide regions is formed in the interlayer insulating film. A Ti (titanium) film covering the inner surface of the hole is formed by a chemical vapor deposition method. At least a surface of the Ti film is nitrided so as to forma barrier metal film covering the inner surface. A plug is formed to fill the through hole via the barrier metal film.
    Type: Application
    Filed: March 7, 2012
    Publication date: June 28, 2012
    Applicant: Renesas Electronics Corporation
    Inventors: Kazuhito ICHINOSE, Yukari Imai
  • Patent number: 8158473
    Abstract: To provide a semiconductor device which can reduce an electrical resistance between a plug and a silicide region, and a manufacturing method thereof. At least one semiconductor element having a silicide region, is formed over a semiconductor substrate. An interlayer insulating film is formed over the silicide region. A through hole having an inner surface including a bottom surface comprised of the silicide regions is formed in the interlayer insulating film. A Ti(titanium) film covering the inner surface of the hole is formed by a chemical vapor deposition method. At least a surface of the Ti film is nitrided so as to form a barrier metal film covering the inner surface. A plug is formed to fill the through hole via the barrier metal film.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: April 17, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuhito Ichinose, Yukari Imai
  • Patent number: 8058166
    Abstract: A method of manufacturing a semiconductor device according to the present invention includes the steps of introducing first impurities of a first conductivity type into a main surface of a semiconductor substrate 1 to form a first impurity region, introducing second impurities of a second conductivity type to form a second impurity region, forming a first nickel silicide film on the first impurity region and forming a second nickel silicide film on the second impurity region, removing an oxide film formed on each of the first and second nickel silicide films by using a mixed gas having an NH3 gas and a gas containing a hydrogen element mixed therein, and forming a first conducting film on the first nickel silicide film and forming a second conducting film on the second nickel silicide film, with the oxide film removed.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: November 15, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuhito Ichinose, Akie Yutani
  • Publication number: 20110221063
    Abstract: A process for burying a tungsten member into a blind hole formed in a wafer, in which blind hole a through via is to be made. Film-formation (for forming the tungsten member) is carried out to position, at the periphery of the wafer, the outer circumference of the tungsten member inside the outer circumference of a barrier metal beneath the tungsten film. This process makes it possible to bury the tungsten member, which may be relatively thin, into the blind hole, which may be relatively large, so as to decrease a warp of the wafer and further prevent an underlying layer beneath the tungsten member from being peeled at the periphery of the wafer.
    Type: Application
    Filed: March 11, 2011
    Publication date: September 15, 2011
    Applicant: Renesas Electronics Corporation
    Inventors: Kazuhito Ichinose, Kotaro Kihara, Tatsunori Murata
  • Publication number: 20110027982
    Abstract: A method of manufacturing a semiconductor device according to the present invention includes the steps of introducing first impurities of a first conductivity type into a main surface of a semiconductor substrate 1 to form a first impurity region, introducing second impurities of a second conductivity type to form a second impurity region, forming a first nickel silicide film on the first impurity region and forming a second nickel silicide film on the second impurity region, removing an oxide film formed on each of the first and second nickel silicide films by using a mixed gas having an NH3 gas and a gas containing a hydrogen element mixed therein, and forming a first conducting film on the first nickel silicide film and forming a second conducting film on the second nickel silicide film, with the oxide film removed.
    Type: Application
    Filed: October 13, 2010
    Publication date: February 3, 2011
    Applicant: Renesas Electronics Corporation
    Inventors: Kazuhito ICHINOSE, Akie YUTANI
  • Patent number: 7834404
    Abstract: A method of manufacturing a semiconductor device according to the present invention includes the steps of introducing first impurities of a first conductivity type into a main surface of a semiconductor substrate 1 to form a first impurity region, introducing second impurities of a second conductivity type to form a second impurity region, forming a first nickel silicide film on the first impurity region and forming a second nickel silicide film on the second impurity region, removing an oxide film formed on each of the first and second nickel silicide films by using a mixed gas having an NH3 gas and a gas containing a hydrogen element mixed therein, and forming a first conducting film on the first nickel silicide film and forming a second conducting film on the second nickel silicide film, with the oxide film removed.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: November 16, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuhito Ichinose, Akie Yutani
  • Publication number: 20100200928
    Abstract: To provide a semiconductor device which can reduce an electrical resistance between a plug and a silicide region, and a manufacturing method thereof. At least one semiconductor element having a silicide region, is formed over a semiconductor substrate. An interlayer insulating film is formed over the silicide region. A through hole having an inner surface including a bottom surface comprised of the silicide regions is formed in the interlayer insulating film. A Ti(titanium) film covering the inner surface of the hole is formed by a chemical vapor deposition method. At least a surface of the Ti film is nitrided so as to form a barrier metal film covering the inner surface. A plug is formed to fill the through hole via the barrier metal film.
    Type: Application
    Filed: February 2, 2010
    Publication date: August 12, 2010
    Inventors: Kazuhito ICHINOSE, Yukari Imai
  • Publication number: 20090321848
    Abstract: A method of manufacturing a semiconductor device according to the present invention includes the steps of introducing first impurities of a first conductivity type into a main surface of a semiconductor substrate 1 to form a first impurity region, introducing second impurities of a second conductivity type to form a second impurity region, forming a first nickel silicide film on the first impurity region and forming a second nickel silicide film on the second impurity region, removing an oxide film formed on each of the first and second nickel silicide films by using a mixed gas having an NH3 gas and a gas containing a hydrogen element mixed therein, and forming a first conducting film on the first nickel silicide film and forming a second conducting film on the second nickel silicide film, with the oxide film removed.
    Type: Application
    Filed: September 9, 2009
    Publication date: December 31, 2009
    Applicant: Renesas Technology Corp.
    Inventors: Kazuhito Ichinose, Akie Yutani
  • Patent number: 7598171
    Abstract: A method of manufacturing a semiconductor device according to the present invention includes the steps of introducing first impurities of a first conductivity type into a main surface of a semiconductor substrate 1 to form a first impurity region, introducing second impurities of a second conductivity type to form a second impurity region, forming a first nickel silicide film on the first impurity region and forming a second nickel silicide film on the second impurity region, removing an oxide film formed on each of the first and second nickel silicide films by using a mixed gas having an NH3 gas and a gas containing a hydrogen element mixed therein, and forming a first conducting film on the first nickel silicide film and forming a second conducting film on the second nickel silicide film, with the oxide film removed.
    Type: Grant
    Filed: January 4, 2007
    Date of Patent: October 6, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Kazuhito Ichinose, Akie Yutani
  • Publication number: 20070173050
    Abstract: A barrier metal film such as a TiN film is formed in a contact hole or a via hole. Then, a W nucleation film is formed on the barrier metal film by CVD that reduces WF6 gas with B2H6 gas. Subsequently, a W plug is formed as a contact plug or a via plug on the W nucleation film by CVD.
    Type: Application
    Filed: January 19, 2007
    Publication date: July 26, 2007
    Inventors: Kazuhito Ichinose, Akie Yutani