Abstract: When a high-level bus converter receives a normal request from any one of a plurality of intermediate-level bus converters, the high-level bus converter converts the normal request into a retry response and sends the retry response to the intermediate-level bus converter, if a normal response buffer is busy. When the high-level bus converter receives an urgent request, the high-level bus converter sends a normal response in response to the urgent request to the intermediate-level bus converter. Each of a plurality of low-level bus converters issues a normal request, converts, when a retry response is received, the retry response into an urgent request, and reissues a request as the urgent request. When a plurality of urgent requests compete with each other for being processed, each of the plurality of intermediate-level bus converters arbitrates among the plurality of urgent requests, and directly transfers a winner urgent request to the high-level bus converter.

Abstract: In an information processing system comprising a plurality of processor units each of which comprises a memory unit, an execution processor, an information transfer unit, and a bus line connected to one another, the memory unit has a control information area and a data area for storing a control information signal and a main data signal, respectively, and a saving area for saving the main data signal which is stored as a copied signal of the data signal. When the copied signal is saved into the saving area, an information transfer unit receives, through the bus line, the main data signal which is read out of the memory unit and which is transferred to the other processor unit. An additional data signal is produced by the other processor unit and stored through the information transfer unit into the saving area.