Patents by Inventor Kazuhito Nishimura
Kazuhito Nishimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11972619Abstract: An information processing device includes: a storage configured to store display region information and a count value, the display region information indicating a position of a predetermined display region in a first image corresponding to image data, the count value indicating frequency of display of each predetermined region in the first image; and a processor including hardware. The processor is configured to, based on the image data and an instruction signal for selecting the display region, generate a display image corresponding to the display region that is selected by the instruction signal, determine whether the display region information meets a first condition, add a predetermined value to the count value of the region on which it is determined that the first condition is met, and set, for a region of interest, a region that draws an interest in the first image based on the count value.Type: GrantFiled: August 6, 2021Date of Patent: April 30, 2024Assignee: Evident CorporationInventors: Nobuyuki Watanabe, Hidetoshi Nishimura, Kazuhito Horiuchi
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Publication number: 20160343885Abstract: Provided is a photoelectric conversion device with an excellent conversion efficiency in which a series resistance between a semiconductor substrate and an electrode is reduced. The photoelectric conversion device includes a semiconductor substrate; a first conductivity region formed on the semiconductor substrate; and an electrode electrically connected to the first conductivity region, in which the first conductivity region includes an electrode region which faces the electrode, and crystal defects in the semiconductor substrate which faces the electrode region.Type: ApplicationFiled: November 21, 2014Publication date: November 24, 2016Inventors: Yoshiyuki NASUNO, Kazuhito NISHIMURA, Takayuki ISAKA, Shinya HONDA
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Patent number: 9040815Abstract: A thin-film solar cell includes a cell having a transparent electrode layer, a photoelectric conversion layer, and a back electrode layer stacked on a transparent insulation substrate. A plurality of cells are connected in series to constitute a cell string. A bus bar is arranged on the back electrode layer of an end cell constituting the cell string. The thin-film solar cell has a photoelectric conversion layer on a series-connection direction end of the transparent electrode layer. In plan view, a series-connection direction end of the back electrode layer at an end of the cell string and the series-connection direction end of the transparent electrode layer at the end of the cell string do not overlap, while the bus bar and the transparent electrode layer at the end cell constituting the cell string overlap at least partially. A method of fabricating the thin-film solar cell is provided.Type: GrantFiled: September 27, 2011Date of Patent: May 26, 2015Assignee: Sharp Kabushiki KaishaInventors: Tohru Takeda, Kazuhito Nishimura
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Publication number: 20150140726Abstract: A transparent conductive substrate (1) in which a transparent conductive film (12) is placed on a light-transmissive base plate (11) is brought into a reaction chamber of a plasma apparatus without being rinsed (Step (a)) and the transparent conductive film (12) is treated with plasma using a CH4 gas and an H2 gas (Step (b)). After Step (b), semiconductor devices are deposited on the transparent conductive film (12) in series (Steps (c) and (d)) and a semiconductor device (10) is manufactured (Step (e)).Type: ApplicationFiled: May 21, 2013Publication date: May 21, 2015Inventors: Shinya Honda, Yoshiyuki Nasuno, Kazuhito Nishimura, Atsushi Tomyo, Takashi Yamada
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Publication number: 20150101658Abstract: A photovoltaic device (10) includes a photovoltaic layer (3) in which a p-type semiconductor layer (31), an i-type semiconductor layer (32), and an n-type semiconductor layer (33) are successively stacked. The p-type semiconductor layer (31) is formed from a p-type thin silicon films (311 to 313). The p-type thin silicon films (311 and 312) are formed by depositing silicon thin films having a p-type conductivity type and then by nitriding the silicon thin films using pulse power in which a 100 Hz to 1 kHz low-frequency pulse power is superimposed on a 1 MHz and 50 MHz high-frequency power as plasma excitation power, and using conditions in which the density of the high-frequency power is 100 to 300 mW/cm2, the pressure during plasma processing is 300 to 600 Pa, and the substrate temperature during plasma processing is 140° C. to 190° C. The p-type thin silicon film (313) is deposited under the above conditions.Type: ApplicationFiled: April 15, 2013Publication date: April 16, 2015Inventors: Kazuhito Nishimura, Yoshiyuki Nasuno, Shinya Honda, Takashi Yamada
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Patent number: 8957300Abstract: A substrate 1 for a photoelectric conversion device includes a first transparent conductive layer 5 formed on at least a part of the surface region of a transparent substrate 3, the first transparent conductive layer 5 having at least an opening portion 7 exposing the substrate 3.Type: GrantFiled: January 7, 2005Date of Patent: February 17, 2015Assignee: Sharp Kabushiki KaishaInventors: Yoshiyuki Nasuno, Noriyoshi Kohama, Kazuhito Nishimura, Takashi Hayakawa
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Publication number: 20140248733Abstract: The present invention provides a method of manufacturing a photoelectric conversion device for forming a semiconductor layer on a substrate by the plasma CVD method. The method includes a first plasma processing step in which a processing temperature reaches a first temperature; a second plasma processing step in which the processing temperature reaches a second temperature; a temperature regulating step of lowering the processing temperature to a third temperature lower than the first temperature and the second temperature after the first plasma processing step and before the second plasma processing step; and a temperature raising step of raising the processing temperature from the third temperature to the second temperature. The first plasma processing step, the temperature regulating step, the temperature raising step, and the second plasma processing step are carried out within the same reaction chamber.Type: ApplicationFiled: September 27, 2012Publication date: September 4, 2014Inventors: Shinya Honda, Yoshiyuki Nasuno, Takashi Yamada, Kazuhito Nishimura
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Patent number: 8705251Abstract: A bidirectional DC/DC converter includes a bidirectional DC/AC conversion circuit including a push-pull circuit connected between voltage terminals and a winding and having a switching element and a switching element coupled to opposing ends of the winding respectively, and an up-conversion circuit coupled to the push-pull circuit and the voltage terminals, and the up-conversion circuit includes an inductor for allowing passage of a current through the winding, the switching element in an ON state and the switching element in an ON state owing to stored magnetic energy, and a switching element forming a current path going through the voltage terminal, the inductor and the voltage terminal but not through the switching element and the switching element as it is turned on.Type: GrantFiled: April 8, 2009Date of Patent: April 22, 2014Assignee: Sharp Kabushiki KaishaInventors: Ryoji Matsui, Kazuhito Nishimura
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Patent number: 8578184Abstract: A power control system includes a distribution unit distributing power supplied from a power system to a plurality of power demanding facilities, and a measurement unit measuring a value of running power between the power system and the distribution unit. A power control instruction is transmitted to a power demanding facility in the event of the condition of TLP<K1 (K1 indicates a threshold value used to detect reverse power flow) is established when the running power flowing from the power system towards the distribution unit is taken as a positive value. The power control instruction instructs a power storage device performing a discharging process to suppress the amount of power supplied in the direction towards the power system, and instructs a power storage device currently performing a charging process to increase the amount of power charged in a corresponding storage battery.Type: GrantFiled: June 16, 2009Date of Patent: November 5, 2013Assignee: Sharp Kabushiki KaishaInventors: Kazuhito Nishimura, Kazuo Yamada
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Publication number: 20130180567Abstract: A thin-film solar cell includes a cell having a transparent electrode layer, a photoelectric conversion layer, and a back electrode layer stacked on a transparent insulation substrate. A plurality of cells are connected in series to constitute a cell string. A bus bar is arranged on the back electrode layer of an end cell constituting the cell string. The thin-film solar cell has a photoelectric conversion layer on a series-connection direction end of the transparent electrode layer. In plan view, a series-connection direction end of the back electrode layer at an end of the cell string and the series-connection direction end of the transparent electrode layer at the end of the cell string do not overlap, while the bus bar and the transparent electrode layer at the end cell constituting the cell string overlap at least partially. A method of fabricating the thin-film solar cell is provided.Type: ApplicationFiled: September 27, 2011Publication date: July 18, 2013Applicant: Sharp Kabushiki KaishaInventors: Tohru Takeda, Kazuhito Nishimura
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Publication number: 20130081685Abstract: A photoelectric conversion device including a substrate and a pin type photoelectric conversion layer disposed on the surface of the substrate is provided. The pin type photoelectric conversion layer includes a first pin type photoelectric conversion layer formed by stacking a p type semiconductor layer, an i type semiconductor layer serving as an amorphous semiconductor layer and an n type semiconductor layer. The first pin type photoelectric conversion layer includes the first portion located on a part of the surface of the substrate and the second portion located on another part of the surface of the substrate. The first portion is higher in concentration of at least one impurity element selected from oxygen, nitrogen and carbon than the second portion. The first portion is less in thickness than the second portion.Type: ApplicationFiled: February 17, 2011Publication date: April 4, 2013Inventors: Kazuhito Nishimura, Yoshiyuki Nasuno, Takanori Nakano
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Patent number: 8362648Abstract: An electric power supply system is provided for feeding an output of a DC power source to a load at high efficiency and, without complicated controlling, for allowing for interchange of electric power among a commercial power system, a DC power source and a load. An electric power supply system includes a DC bus line for connecting a DC generator, a load and system power. The electric power supply system comprises a DC/DC converter connected between the DC generator and the DC bus line for controlling an output voltage to the DC bus line at a voltage V1; an inverter connected between the system power and the DC bus line for operating a control in response to an input voltage V2 from the DC bus line; and an AC/DC converter connected between the system power and the DC bus line for controlling an output voltage to the DC bus line at a voltage V3, wherein the respective voltages are set as V1>V2>V3.Type: GrantFiled: November 25, 2008Date of Patent: January 29, 2013Assignee: Sharp Kabushiki KaishaInventors: Ryoji Matsui, Kazuhito Nishimura
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Publication number: 20130000721Abstract: A photoelectric conversion device includes a substrate and a transparent, electrically conductive film covering at least a portion of a major surface of the substrate and having an irregular geometry on a surface thereof closer to a semiconductor layer. Furthermore, the photoelectric conversion device includes a first conduction type semiconductor layer covering at least a portion of the irregular geometry of the transparent, electrically conductive film, and a light absorption layer covering the first conduction type semiconductor layer. The irregular geometry has a bump having a maximum height equal to or larger than 50 nm and equal to or smaller than 1200 nm. The bump has a surface having a submicron recess having local peaks having a spacing equal to or larger than 2 nm and equal to or smaller than 25 nm.Type: ApplicationFiled: March 31, 2010Publication date: January 3, 2013Inventors: Yoshiyuki Nasuno, Kazuhito Nishimura, Hiroki Tanimura, Kei Kajihara
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Patent number: 8307782Abstract: A deposition apparatus includes: a first electrode for placing a processing object; a second electrode for generating plasma with the first electrode, the second electrode being opposed to the first electrode; and a cooling part for cooling the processing object, wherein between the processing object and the cooling part, as compared with a thermal resistance between a central part of the processing object and the cooling part, a thermal resistance between a peripheral part peripheral to the central part and the cooling part is small.Type: GrantFiled: December 23, 2008Date of Patent: November 13, 2012Assignees: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.Inventors: Kazuhito Nishimura, Hideki Sasaoka
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Publication number: 20120280242Abstract: There is provided a semiconductor film formed on a surface of a substrate and containing a crystalline substance, wherein the semiconductor film has a central region including a center of a surface of the semiconductor film and a peripheral region located around the central region, and a crystallization ratio in the peripheral region of the semiconductor film is higher than a crystallization ratio in the central region. There is also provided a photoelectric conversion device including the semiconductor film.Type: ApplicationFiled: December 28, 2010Publication date: November 8, 2012Inventors: Yoshiyuki Nasuno, Kazuhito Nishimura, Takanori Nakano
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Patent number: 8294435Abstract: A power supply apparatus converting electric power stored in a first power storage unit into a prescribed voltage for supply to a load includes: a power storage unit-side terminal coupled to the first power storage unit; a second power storage unit; a load-side terminal coupled to the load; a converter unit for increasing output voltage of the first power storage unit to a first voltage and outputting the first voltage to the load-side terminal at a time of discharging of the first power storage unit; a step-up circuit for increasing the output voltage of the first power storage unit and supplying the increased voltage to the second power storage unit; and a backflow prevention circuit arranged between the second power storage unit and the load-side terminal to allow current to flow from the second power storage unit to the load-side terminal and block current flowing from the load-side terminal to the second power storage unit.Type: GrantFiled: March 31, 2008Date of Patent: October 23, 2012Assignee: Sharp Kabushiki KaishaInventor: Kazuhito Nishimura
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Publication number: 20120080774Abstract: The semiconductor of the present invention has iron sulfide and a forbidden band control element contained in the iron sulfide. The forbidden band control element has a property capable of controlling the forbidden band of iron sulfide on the basis of the number density of the forbidden band control element in the iron sulfide. An n-type semiconductor is manufactured by incorporating a group 13 element of the IUPAC system into iron sulfide. Moreover, a p-type semiconductor is manufactured by incorporating a group Ia element into iron sulfide. A semiconductor junction device or a photoelectric converter is manufactured by using the n-type semiconductor and the p-type semiconductor.Type: ApplicationFiled: December 7, 2011Publication date: April 5, 2012Applicant: SHARP KABUSHIKI KAISHAInventors: Yoshiyuki NASUNO, Noriyoshi Kohama, Kazuhito Nishimura
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Patent number: 8106535Abstract: A reliable power conditioner comprises: a power converting circuit for converting direct-current power obtained from a direct-current power source to alternating-current power of a commercial power system; a charger/discharger circuit for charging the direct-current power obtained from the direct-current power source to an accumulator or discharging the direct-current power stored in the accumulator; a control circuit for controlling the power converting circuit and the charger/discharger circuit; and a power source selecting circuit for selecting at least one of first, second, and third power source circuits and supplying power to the control circuit.Type: GrantFiled: August 3, 2007Date of Patent: January 31, 2012Assignee: Sharp Kabushiki KaishaInventor: Kazuhito Nishimura
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Patent number: 8093684Abstract: The semiconductor of the present invention has iron sulfide and a forbidden band control element contained in the iron sulfide. The forbidden band control element has a property capable of controlling the forbidden band of iron sulfide on the basis of the number density of the forbidden band control element in the iron sulfide. An n-type semiconductor is manufactured by incorporating a group 13 element of the IUPAC system into iron sulfide. Moreover, a p-type semiconductor is manufactured by incorporating a group Ia element into iron sulfide. A semiconductor junction device or a photoelectric converter is manufactured by using the n-type semiconductor and the p-type semiconductor.Type: GrantFiled: January 9, 2007Date of Patent: January 10, 2012Assignee: Sharp Kabushiki KaishaInventors: Yoshiyuki Nasuno, Noriyoshi Kohama, Kazuhito Nishimura
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Patent number: 8035291Abstract: An electron emission film having a pattern of diamond in X-ray diffraction and formed of a plurality of diamond fine grains having a grain diameter of 5 nm to 10 nm is formed on a substrate. The electron emission film can restrict the field intensity to a low level when it causes an emission current to flow, and has a uniform electron emission characteristic.Type: GrantFiled: May 13, 2010Date of Patent: October 11, 2011Assignees: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.Inventors: Kazuhito Nishimura, Hideki Sasaoka