Abstract: According to one embodiment, an apparatus is capable of exchanging a frame with an external apparatus in a packet mode of a serial attached small computer system interface (SAS). The external apparatus includes a scrambler. The apparatus includes a descrambler and a controller. The descrambler is configured to descramble frame data scrambled by the scrambler. The controller is configured to, in a case where first frame data is received from the external apparatus, synchronize the descrambler with the scrambler using the first frame data and a first value that is to be scrambled by the scrambler to obtain the first frame data.

Abstract: A memory system includes a non-volatile memory, a data buffer in which data read out from the nonvolatile memory are stored prior to transmission to an initiator that is requesting the data, a port through which the initiator sends a request for the data and through which the data in the data buffer are transmitted to the initiator. When the port is connected to a first initiator at a time both first data requested by the first initiator and second data requested by a second initiator are stored in the data buffer and the second data become ready for transmission prior to the first data, the second data are transmitted through the port prior to the first data.

Abstract: According to one embodiment, an apparatus is capable of exchanging a frame with an external apparatus in a packet mode of a serial attached small computer system interface (SAS). The external apparatus includes a scrambler. The apparatus includes a descrambler and a controller. The descrambler is configured to descramble frame data scrambled by the scrambler. The controller is configured to, in a case where first frame data is received from the external apparatus, synchronize the descrambler with the scrambler using the first frame data and a first value that is to be scrambled by the scrambler to obtain the first frame data.

Abstract: A semiconductor storage device includes at least two nonvolatile semiconductor memories, a buffer in which data received from a host and to be written to the nonvolatile semiconductor memories in response to a write command received from the host can be temporarily stored, and a controller connected to the nonvolatile semiconductor memories and configured to transfer data stored in the buffer to a number N of the nonvolatile semiconductor memories in parallel. The number N is set according to a reception of data from the host, and N is greater than or equal to 1 and less than or equal to m, which is the number of nonvolatile semiconductor memories connected to the controller.

Abstract: A storage device includes a nonvolatile memory including a plurality of blocks, and a controller. The controller is configured to retain a logical address range designated by each of a plurality of write commands that were received, and upon each gap of two adjacent logical address ranges of two or more of the write commands being smaller than a first threshold and an entire length of the logical address ranges of said two or more write commands being larger than a second threshold, write data corresponding to one of said two or more write commands in one of the blocks of the nonvolatile memory, as a part of a single data group comprising data corresponding to each of said two or more write commands, such that data that do not form the single data group are not written in said one of the blocks of the nonvolatile memory.

Abstract: A semiconductor storage device includes at least two nonvolatile semiconductor memories, a buffer in which data received from a host and to be written to the nonvolatile semiconductor memories in response to a write command received from the host can be temporarily stored, and a controller connected to the nonvolatile semiconductor memories and configured to transfer data stored in the buffer to a number N of the nonvolatile semiconductor memories in parallel. The number N is set according to a reception of data from the host, and N is greater than or equal to 1 and less than or equal to m, which is the number of nonvolatile semiconductor memories connected to the controller.

Abstract: A storage device includes a nonvolatile memory including a plurality of blocks, and a controller. The controller is configured to retain a logical address range designated by each of a plurality of write commands that were received, and upon each gap of two adjacent logical address ranges of two or more of the write commands being smaller than a first threshold and an entire length of the logical address ranges of said two or more write commands being larger than a second threshold, write data corresponding to one of said two or more write commands in one of the blocks of the nonvolatile memory, as a part of a single data group comprising data corresponding to each of said two or more write commands, such that data that do not form the single data group are not written in said one of the blocks of the nonvolatile memory.

Abstract: A memory device includes a nonvolatile memory unit a volatile memory unit, and a memory controller. When the memory controller receives a first read command designating a first address range of the nonvolatile memory from a host, the memory controller reads data of a second address range that includes and is longer than the first address range from the nonvolatile memory unit, stores the data of the second address range in the volatile memory unit, and then transfers the data of the first address range from the volatile memory unit to the host. When the memory controller receives a second read command designating a third address range that follows the first address range and is within the second address range, after receiving the first read command, the memory controller transfers corresponding data that has been already stored in the volatile memory unit to the host.

Abstract: According to one embodiment, a system includes first to third managers and a storage unit. The first manager generates read requests corresponding to read-unit data items read by a read command received from an device, and manages first information indicating the state of transmission of the read-unit data items to the device. The storage unit temporarily stores the read-unit data items read from nonvolatile memories in a random order, based on the read requests. The second manager manages second information indicating whether each read-unit data item has been read from the nonvolatile memories. The third manager transmits, based on the first and second information, the read-unit data items to the device in an order designated by the read command, the read-unit data items being stored in the storage unit in a random order.

Abstract: A memory system includes a non-volatile memory, a data buffer in which data read out from the nonvolatile memory are stored prior to transmission to an initiator that is requesting the data, a port through which the initiator sends a request for the data and through which the data in the data buffer are transmitted to the initiator. When the port is connected to a first initiator at a time both first data requested by the first initiator and second data requested by a second initiator are stored in the data buffer and the second data become ready for transmission prior to the first data, the second data are transmitted through the port prior to the first data.

Abstract: According to one embodiment, a system includes first to third managers and a storage unit. The first manager generates read requests corresponding to read-unit data items read by a read command received from an device, and manages first information indicating the state of transmission of the read-unit data items to the device. The storage unit temporarily stores the read-unit data items read from nonvolatile memories in a random order, based on the read requests. The second manager manages second information indicating whether each read-unit data item has been read from the nonvolatile memories. The third manager transmits, based on the first and second information, the read-unit data items to the device in an order designated by the read command, the read-unit data items being stored in the storage unit in a random order.

Abstract: A memory device includes a nonvolatile memory unit a volatile memory unit, and a memory controller. When the memory controller receives a first read command designating a first address range of the nonvolatile memory from a host, the memory controller reads data of a second address range that includes and is longer than the first address range from the nonvolatile memory unit, stores the data of the second address range in the volatile memory unit, and then transfers the data of the first address range from the volatile memory unit to the host. When the memory controller receives a second read command designating a third address range that follows the first address range and is within the second address range, after receiving the first read command, the memory controller transfers corresponding data that has been already stored in the volatile memory unit to the host.

Abstract: A memory system includes an interface, a storage, and a controller. The interface is configured to connect to a plurality of initiators. The storage is configured to store data. The controller is configured to refer to a connection condition of the interface and transmit data to be transmitted to an initiator being connected from the storage.

Abstract: According to one embodiment, a memory system includes an interface, a storage, and a controller. The interface is configured to connect to a plurality of initiators. The storage is configured to store data. The controller is configured to refer to a connection condition of the interface and transmit data to be transmitted to an initiator being connected from the storage.

Abstract: A storage device of the embodiment includes memory, a control section, a table holding section for managing a table for holding an identifier, a logical address, and a data length based on a read command, an issuing section for issuing the logical address and the data length for each identifier to the control section, a buffer for holding data received from the memory along with the identifier, and an identifier queue for receiving the identifier of a number proportional to a data length when the data of the logical address of the same identifier is received in the buffer. The storage device of the embodiment includes a transfer section for transferring the data corresponding to the identifier received in the buffer to outside when the identifier is held as incomplete readout in the table in order from the identifier at a head of the identifier queue.

Abstract: A storage device of the embodiment includes memory, a control section, a table holding section for managing a table for holding an identifier, a logical address, and a data length based on a read command, an issuing section for issuing the logical address and the data length for each identifier to the control section, a buffer for holding data received from the memory along with the identifier, and an identifier queue for receiving the identifier of a number proportional to a data length when the data of the logical address of the same identifier is received in the buffer. The storage device of the embodiment includes a transfer section for transferring the data corresponding to the identifier received in the buffer to outside when the identifier is held as incomplete readout in the table in order from the identifier at a head of the identifier queue.

Abstract: Aspects of the present embodiment are related to a power supply voltage supply circuit and the disk apparatus that are capable of reducing power consumption in data writing and reading. The power supply voltage supply circuit includes a data processing unit writing data onto a disk medium and/or reading data from the disk medium=having a plurality of zones assigned a cylinder number, a data input-output unit transmitting data to the data processing unit at a transfer rate in accordance with the zones, a power supply voltage supply unit supplying a voltage to the data input-output unit and a control unit controlling the power supply voltage supply unit in order to supply the voltage in accordance with the transfer rate.

Abstract: According to one embodiment, a power supply voltage adjustment circuit includes a determination module and a voltage controller. The determination module determines whether a head is positioned on a data area specified by a command received from a host based on the relationship between the position of the head and the command. The head reads data from or writes data to an information recording medium. When the head is determined not to be positioned on the data area specified by the command, the voltage controller adjusts a target control value of a power supply voltage supplied to a read channel that exchanges information with the head according to a timing from a time point when a servo mark on the information recording medium is detected.

Abstract: Aspects of the present embodiment are related to a power supply voltage supply circuit and the disk apparatus that are capable of reducing power consumption in data writing and reading. The power supply voltage supply circuit includes a data processing unit writing data onto a disk medium and/or reading data from the disk medium=having a plurality of zones assigned a cylinder number, a data input-output unit transmitting data to the data processing unit at a transfer rate in accordance with the zones, a power supply voltage supply unit supplying a voltage to the data input-output unit and a control unit controlling the power supply voltage supply unit in order to supply the voltage in accordance with the transfer rate.