Abstract: A semiconductor package according to the present disclosure includes: a plurality of semiconductor chips that include a system on chip (SoC) in which a plurality of integrated circuits including a processor core and a microcomputer are integrated on a single chip; a power management integrated circuit (IC) for performing power management on the plurality of semiconductor chips; a plurality of shunt resistors each of which is mounted in series on a different one of power wires connecting the power management IC and the plurality of semiconductor chips; two output terminals; and a single selector that outputs voltages at both ends of a shunt resistor to an outside via the two output terminals, the shunt resistor being selected from among the plurality of shunt resistors. The power management IC, the plurality of semiconductor chips, the plurality of shunt resistors, and the single selector are mounted inside a single package.

Abstract: A localization system includes: a first data acquisition unit that acquires map data for map creation in a plurality of different time zones; a candidate creation unit that creates the maps based on the map data acquired by the first data acquisition unit, and combines the created maps to create a plurality of synthetic map candidates; a performance calculation unit that calculates a performance value of each of the synthetic map candidates created by the candidate creation unit; a candidate selection unit that selects one synthetic map candidate from among the plurality of synthetic map candidates based on the performance value of the synthetic map candidate calculated by the performance calculation unit; and a localization unit that performs localization of a mobile body based on the synthetic map candidate selected by the candidate selection unit.

Abstract: An autonomous mobile robot includes a first arithmetic unit configured to calculate a course direction based on an own position, a moving-object position, and a moving-object velocity vector, the course direction being a direction in which the autonomous mobile robot should travel, a second arithmetic unit configured to input the own position, the moving-object position, the moving-object velocity vector, and the course direction into a trained model and thereby calculate an estimated position, the trained model being a model that has been trained, the estimated position being a position at which the autonomous mobile robot is estimated to arrive a predetermined time later without colliding with the moving object, a generating unit configured to generate a remaining route from the estimated position to a destination, and a movement control unit configured to control a movement to the destination based on the course direction and the remaining route.

Abstract: A semiconductor memory device includes a data bus terminal group for outputting read data to an external device or inputting write data from an external device, a first terminal from or into which 1-bit data is output or input, a DBI circuit that executes a Data Bus Inversion (DBI) function, an error detection circuit that detects an internal error, and an information superimposing circuit that superimposes predetermined output information onto the 1-bit data to be output from the first terminal and the read data to be output from the data bus terminal group. The predetermined output information includes first output information indicating whether or not an output bit pattern of the data bus terminal group is inverted, and second output information indicating whether or not an internal error has been detected by the error detection circuit.

Abstract: A memory controller controls access to a Synchronous Dynamic Random Access Memory (SDRAM) including banks. The memory controller includes: a receiver that receives a memory access request from an access master; a selector that selects one of a first issue mode and a second issue mode each related to command issuing; and an issuer that issues a command sequence to the SDRAM in response to the memory access request, in accordance with the one of the first issue mode and the second issue mode which is selected by the selector. The first issue mode is a mode in which an activation command for activating a bank among the banks is issued in continuous clock cycles without dividing the activation command, the activation command being included in the command sequence. The second issue mode is a mode in which the activation command is divided and issued in non-continuous clock cycles.

Abstract: An autonomous mobile robot includes a first arithmetic unit configured to calculate a course direction based on an own position, a moving-object position, and a moving-object velocity vector, the course direction being a direction in which the autonomous mobile robot should travel, a second arithmetic unit configured to input the own position, the moving-object position, the moving-object velocity vector, and the course direction into a trained model and thereby calculate an estimated position, the trained model being a model that has been trained, the estimated position being a position at which the autonomous mobile robot is estimated to arrive a predetermined time later without colliding with the moving object, a generating unit configured to generate a remaining route from the estimated position to a destination, and a movement control unit configured to control a movement to the destination based on the course direction and the remaining route.

Abstract: A semiconductor memory device includes a data bus terminal group for outputting read data to an external device or inputting write data from an external device, a first terminal from or into which 1-bit data is output or input, a DBI circuit that executes a Data Bus Inversion (DBI) function, an error detection circuit that detects an internal error, and an information superimposing circuit that superimposes predetermined output information onto the 1-bit data to be output from the first terminal and the read data to be output from the data bus terminal group. The predetermined output information includes first output information indicating whether or not an output bit pattern of the data bus terminal group is inverted, and second output information indicating whether or not an internal error has been detected by the error detection circuit.

Abstract: A command control system is provided which is configured to optimally set an output timing of a RAS command and an output timing of a CAS command for access requests different from each other. The command control system is configured to, when an output timing of a second RAS command is set in a first cycle time period which is a cycle starting from the reference time point, determine whether or not the second RAS command is output to a storage device in the first cycle time period in accordance with whether or not an output timing of a first CAS command is set in a second cycle time period constituted by a prescribed number of the cycles subsequent to the reference time point.

Abstract: An environment arrangement robot includes a map creation unit that divides the target space into a plurality of cell spaces and provides an evaluation value to each of the cell spaces, in which the evaluation value indicates a probability of whether or not there is an object in the corresponding cell space, and an environment change unit that changes, among the plurality of cell spaces, a specific cell space having the evaluation value within a range evaluated that the probability of whether or not there is an object in the specific cell is low in such a way that the probability that the object is present will become greater or change a surrounding cell space in such a way that the specific cell space will be excluded from the measurement by the distance sensor.

Abstract: An environment arrangement robot includes a map creation unit that divides the target space into a plurality of cell spaces and provides an evaluation value to each of the cell spaces, in which the evaluation value indicates a probability of whether or not there is an object in the corresponding cell space, and an environment change unit that changes, among the plurality of cell spaces, a specific cell space having the evaluation value within a range evaluated that the probability of whether or not there is an object in the specific cell is low in such a way that the probability that the object is present will become greater or change a surrounding cell space in such a way that the specific cell space will be excluded from the measurement by the distance sensor.

Abstract: A three-dimensional object recognition apparatus according to the invention includes: an omnidirectional sensor that measures surrounding objects in all directions, and generates positional information capable of specifying positions of the objects as a result of the measurement; a three-dimensional measurement device that measures an object within a certain measurement range among the surrounding objects, and generates three-dimensional shape information capable of specifying a three-dimensional shape of the object as a result of the measurement; and a control unit that updates a shape to be recognized as the three-dimensional shape of the object based on the three-dimensional shape information generated by the three-dimensional measurement device when the object is within the measurement range of the three-dimensional measurement device.

Abstract: A three-dimensional object recognition apparatus according to the invention includes: an omnidirectional sensor that measures surrounding objects in all directions, and generates positional information capable of specifying positions of the objects as a result of the measurement; a three-dimensional measurement device that measures an object within a certain measurement range among the surrounding objects, and generates three-dimensional shape information capable of specifying a three-dimensional shape of the object as a result of the measurement; and a control unit that updates a shape to be recognized as the three-dimensional shape of the object based on the three-dimensional shape information generated by the three-dimensional measurement device when the object is within the measurement range of the three-dimensional measurement device.

Abstract: A manufacturing method of a joint panel includes: joining an outer panel to an inner panel by applying an adhesive to an outer edge of the outer panel; performing electrodeposition coating on a surface of the outer panel of the joint panel in which the outer panel is joined to the inner panel; and burning, onto the outer panel, a coating film formed on the surface of the outer panel by the electrodeposition coating. The adhesive used herein is a room temperature curing adhesive that does not flow at the time of the burning.

Abstract: A test pattern generation circuit outputs a test pattern during a clock phase adjustment period. A flip-flop circuit latches the test pattern at the fall of a shift clock and outputs it as a test pattern. A latch miss detection circuit outputs a latch miss detection signal indicating presence/absence of a latch miss generation according to the test pattern and a delay shift clock. A clock phase controller delays the shift clock according to the latch miss detection signal, thereby outputting a delay shift clock.

Abstract: The memory control circuit has an access count setting circuit and a DRAM access control circuit. The access count setting circuit receives a minimum activation interval time for different rows in the same bank of the SDRAM, an operating speed, and the number of banks, and calculates an optimal number of readings or writings to each bank. The DRAM access control circuit generates a command sequence and an address for reading or writing a image signal to the SDRAM.

Abstract: A test pattern generation circuit (100) outputs a test pattern (TP) during a clock phase adjustment period. A flip-flop circuit (110) latches the test pattern (TP) at the fall of a shift clock (SCK) and outputs it as a test pattern (Tpa). A latch miss detection circuit (130) outputs a latch miss detection signal (LM) indicating presence/absence of a latch miss generation according to the test pattern (TPa) and a delay shift clock (DSCK). A clock phase control section (120) delays the shift clock (SCK) according to the latch miss detection signal (LM), thereby outputting a delay shift clock (DSCK).

Abstract: A vertical HPF and a horizontal HPF receive a video signal 101, and extract only a high frequency component in the vertical/horizontal directions, respectively. Absolute value taking parts take an absolute value of the high frequency components, respectively, and change their values to positive values. A horizontal accumulating/adding part and a vertical accumulating/adding part accumulate/add an input signal so as to output a vertical one-dimensional signal and a horizontal one-dimensional signal, respectively, each periodically having a peak value in the respective vertical and horizontal directions. A horizontal peak detecting part detects a horizontal peak position according to the horizontal one-dimensional signal. A vertical peak detecting part detects a vertical peak position according to the vertical one-dimensional signal and identifies a format thereof.

Abstract: An object is to provide a vertical contour correcting device for a video signal which reduces noise without deteriorating effect of the entire contour correction. A vertical contour correcting device (VCP1) which corrects vertical contour components (S1v, S1v′) of a video signal (S1) with a given quantity of correction (K) to enhance the vertical contour (Ev) of the video signal (S1) comprises a vertical contour component extracting device (3) for detecting said vertical contour components (S1v, S1v′) from said video signal (S1), a vertical contour component correlation detector (3, 29, 8c, 8d, 4) for detecting correlation between horizontally adjacent vertical contour components (Sb, Sb′, Sb′′) from said detected vertical contour components (S1v, S1v′), and a controller (5) for determining said quantity of correction (K) on the basis of said detected correlation (Sj1), thereby varying the quantity of correction (K) in accordance with the correlation (Sj1).

Abstract: A video signal converter converts a first video signal into a second video signal by changing the number of scanning lines. A horizontal pulse synchronized with the first video signal is fed into a PLL circuit, which generates a first clock signal synchronized with the horizontal pulse. The first video signal undergoes A/D conversion by sampling with the first clock signal. The converter receives a first digital video signal which has undergone the A/D conversion, the first clock signal, the horizontal pulse, and a vertical pulse synchronized with the first video signal, and thus changes a number of scanning lines of the first video signal. The converter, next, writes a second digital video signal into a memory by synchronizing the first clock signal.