Patents by Inventor Kazuhito Tohnoe
Kazuhito Tohnoe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8975188Abstract: A plasma etching method is provided for forming a hole using a first processing gas to etch a silicon layer of a substrate to be processed including a silicon oxide film that is formed into a predetermined pattern. The method includes a first depositing step (S11) of depositing a protective film on a surface of the silicon oxide film using a second processing gas containing carbon monoxide gas, a first etching step (S12) of etching the silicon layer using the first processing gas, a second depositing step (S13) of depositing the protective film on a side wall of a hole etched by the first etching step using the second processing gas, and a second etching step (S14) of further etching the silicon layer using the first processing gas. The second depositing step (S13) and the second etching step (S14) are alternately repeated at least two times each.Type: GrantFiled: July 10, 2012Date of Patent: March 10, 2015Assignee: Tokyo Electron LimitedInventors: Yusuke Hirayama, Kazuhito Tohnoe
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Patent number: 8975191Abstract: There is provided a plasma etching method including a first process of etching an intermediate layer, which contains silicon and nitrogen and is positioned below a resist mask formed on a surface of a substrate, to cause a silicon layer positioned below the intermediate layer to be exposed through the resist mask and the intermediate layer, a second process of subsequently supplying a chlorine gas to the substrate to cause a reaction product to attach onto sidewalls of opening portions of the resist mask and the intermediate layer, and a third process of etching a portion of the silicon layer corresponding to the opening portion of the intermediate layer using a process gas containing sulfur and fluorine to form a recess in the silicon layer.Type: GrantFiled: February 7, 2012Date of Patent: March 10, 2015Assignee: Tokyo Electron LimitedInventors: Kazuhito Tohnoe, Yusuke Hirayama, Yasuyoshi Ishiyama, Wataru Hashizume
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Publication number: 20140227876Abstract: In a semiconductor device manufacturing method having a plasma etching process, a substrate is plasma etched using a resist layer as a mask. The plasma etching process has: a first etching step wherein a mixed gas having a deposition gas and an etching gas mixed at a ratio is introduced into the processing chamber, and the substrate is plasma etched in the mixed gas atmosphere; and a step of repeating multiple times a deposition step, wherein the deposition gas is introduced into the processing chamber, and the plasma-etched substrate is subjected to deposition treatment in an atmosphere having the deposition gas as a main component, and a second etching step, wherein the etching gas is introduced into the processing chamber, and the substrate that has been subjected to the deposition treatment in the deposition step is plasma etched in an atmosphere having the etching gas as a main component.Type: ApplicationFiled: October 5, 2012Publication date: August 14, 2014Applicant: TOKYO ELECTRON LIMITEDInventor: Kazuhito Tohnoe
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Publication number: 20140134846Abstract: A plasma etching method is provided for forming a hole using a first processing gas to etch a silicon layer of a substrate to be processed including a silicon oxide film that is formed into a predetermined pattern. The method includes a first depositing step (S11) of depositing a protective film on a surface of the silicon oxide film using a second processing gas containing carbon monoxide gas, a first etching step (S12) of etching the silicon layer using the first processing gas, a second depositing step (S13) of depositing the protective film on a side wall of a hole etched by the first etching step using the second processing gas, and a second etching step (S14) of further etching the silicon layer using the first processing gas. The second depositing step (S13) and the second etching step (S14) are alternately repeated at least two times each.Type: ApplicationFiled: July 10, 2012Publication date: May 15, 2014Inventors: Yusuke Hirayama, Kazuhito Tohnoe
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Publication number: 20140045338Abstract: There is provided a plasma etching method including a first process of etching an intermediate layer, which contains silicon and nitrogen and is positioned below a resist mask formed on a surface of a substrate, to cause a silicon layer positioned below the intermediate layer to be exposed through the resist mask and the intermediate layer, a second process of subsequently supplying a chlorine gas to the substrate to cause a reaction product to attach onto sidewalls of opening portions of the resist mask and the intermediate layer, and a third process of etching a portion of the silicon layer corresponding to the opening portion of the intermediate layer using a process gas containing sulfur and fluorine to form a recess in the silicon layer.Type: ApplicationFiled: February 7, 2012Publication date: February 13, 2014Inventors: Kazuhito Tohnoe, Yusuke Hirayama, Yasuyoshi Ishiyama, Wataru Hashizume
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Publication number: 20120252210Abstract: A method for forming a semiconductor device with improved electromigration (EM) and stress migration (SM) properties. The method includes providing a planarized patterned substrate containing a copper (Cu) metal surface and a low-k dielectric layer surface, selectively depositing a metal cap layer on the Cu metal surface, and modifying the metal cap layer by exposing the metal cap layer to a process gas containing ammonia (NH3) gas without plasma excitation. The method further includes forming a dielectric barrier film on the modified metal cap layer and on the dielectric layer surface, and exposing the dielectric barrier film to a gaseous oxidizing environment, where the dielectric barrier film and the modified metal cap layer prevent oxidation of the Cu metal surface when the dielectric barrier film is exposed to the gaseous oxidizing environment.Type: ApplicationFiled: March 30, 2011Publication date: October 4, 2012Applicant: Tokyo Electron LimitedInventor: Kazuhito Tohnoe
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Patent number: 8178439Abstract: A method is provided for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices. In one embodiment, the method includes providing a planarized patterned substrate containing metal surfaces and dielectric layer surfaces with a residue formed thereon, removing the residue from the planarized patterned substrate, and depositing metal-containing cap layers selectively on the metal surfaces by exposing the dielectric layer surfaces and the metal surfaces to a deposition gas containing metal-containing precursor vapor. The removing includes treating the planarized patterned substrate containing the residue with a reactant gas containing a hydrophobic functional group, and exposing the treated planarized patterned substrate to a reducing gas.Type: GrantFiled: March 30, 2010Date of Patent: May 15, 2012Assignee: Tokyo Electron LimitedInventors: Kazuhito Tohnoe, Frank M. Cerio, Jr.
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Publication number: 20110244680Abstract: A method is provided for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices. In one embodiment, the method includes providing a planarized patterned substrate containing metal surfaces and dielectric layer surfaces with a residue formed thereon, removing the residue from the planarized patterned substrate, and depositing metal-containing cap layers selectively on the metal surfaces by exposing the dielectric layer surfaces and the metal surfaces to a deposition gas containing metal-containing precursor vapor. The removing includes treating the planarized patterned substrate containing the residue with a reactant gas containing a hydrophobic functional group, and exposing the treated planarized patterned substrate to a reducing gas.Type: ApplicationFiled: March 30, 2010Publication date: October 6, 2011Applicant: TOKYO ELECTRON LIMITEDInventors: Kazuhito Tohnoe, Frank M. Cerio, JR.