Patents by Inventor Kazuhito Yamasaki

Kazuhito Yamasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6625792
    Abstract: A semiconductor design system enhances layout on a semiconductor chip. Module layout positions of an integrated circuit chip are determined based on design information including information for connecting external circuits and modules information for connecting modules, macro information, and chip information. Before initiating detailed layout design of the chip, namely, in a stage where chip specifications are determined and before generation of an RTL description, accurate layout position information of modules are obtained. A determining unit determines a layout position of a module based on design information of information for connecting an external circuit to the module and information for interconnecting the module to other modules, macro information corresponding to a macro within the module and chip information corresponding to the semiconductor chip. A module moving unit moves the module having the associated macro to an area near a side of the semiconductor chip.
    Type: Grant
    Filed: July 20, 2000
    Date of Patent: September 23, 2003
    Assignee: Fujitsu Limited
    Inventor: Kazuhito Yamasaki