Patents by Inventor Kazuichi Oe

Kazuichi Oe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11221783
    Abstract: An apparatus includes a memory that stores information managing whether a writing access to a storing region of a first storing device is present or absent for each of second-sized partial regions obtained by dividing a first-sized storing region by a given value; and a processor configured to: in response to an instruction to migrate first-sized target data from the first storing device to a second storing device having an access speed lower than that of the first storing device, when a number of accessed partial regions in a storing region of the target data is larger than a threshold, migrating the target data in a unit of the first size; otherwise migrating data in the accessed partial regions in a unit of the second size; calculating a first/second migration time periods that the migrations of the first/second size takes; and changing the threshold based on the calculating.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: January 11, 2022
    Assignee: FUJITSU LIMITED
    Inventor: Kazuichi Oe
  • Publication number: 20210263845
    Abstract: An apparatus includes: a first memory; a second memory different in processing speed from the first memory; and a processor comprising a memory controller, the memory controller being connected to the first memory and the second memory and controlling accesses to the first memory and the second memory. The processor being configured to: output a transfer request for data to be transferred from the first memory to the second memory or data to be transferred from the second memory to the first memory; control, based on one or more first accesses to the first memory and the second memory through the memory controller and a data amount to be transferred in a second access to the first memory and the second memory through the memory controller in response to the transfer request, an execution timing of the second access; and execute the second access at the controlled execution timing.
    Type: Application
    Filed: December 8, 2020
    Publication date: August 26, 2021
    Applicant: FUJITSU LIMITED
    Inventors: Kazuichi Oe, Satoshi Imamura, Eiji Yoshida
  • Publication number: 20210157496
    Abstract: An information processing apparatus includes: a memory region; a communication interface that is connected to an access apparatus different from the information processing apparatus; a storage region that the communication interface accesses in response to an access request from the access apparatus; and a processor coupled to the memory region and the storage region, and configured to access the memory region and the storage region, wherein the processor including a memory controller configured to control an access to the memory region and an access to the storage region, and the processor is configured to control, based on a state of one or more first accesses to the memory region and the storage region via the memory controller, a timing of executing a second access to the storage region that the communication interface makes via the memory controller.
    Type: Application
    Filed: October 2, 2020
    Publication date: May 27, 2021
    Applicant: FUJITSU LIMITED
    Inventors: Kazuichi Oe, Satoshi Imamura, Eiji Yoshida
  • Patent number: 11010081
    Abstract: An apparatus monitors an access load state of a plurality of logical volumes of a first storage device, and determines that an access load state of a subset of the plurality of logical volumes has changed from a high load state to a low load state. The apparatus migrates, when the subset of the plurality of logical volumes remains in a low load state after an elapsed setting time since the load state of the subset of the plurality of logical volumes changed from a high load state to a low load state, data stored in the subset of the plurality of logical volumes to a second storage device having an access rate lower than the first storage device.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: May 18, 2021
    Assignee: FUJITSU LIMITED
    Inventor: Kazuichi Oe
  • Publication number: 20200293217
    Abstract: An apparatus includes a memory chat stores information managing whether a writing access to a storing region of a first storing device is present or absent for each of second-sized partial regions obtained by dividing a first-sized storing region by a given value; and a processor configured to: in response to an instruction to migrate first-sized target data from the first storing device to a second storing device having an access speed lower than that of the first storing device, when a number of accessed partial regions in a storing region of the target data is larger than a threshold, migrating the target data in a unit of the first size; otherwise migrating data in the accessed partial regions in a unit of the second size; calculating a first/second migration time periods that the migrations of the fist/second size takes; and changing the threshold based on the calculating.
    Type: Application
    Filed: February 10, 2020
    Publication date: September 17, 2020
    Applicant: FUJITSU LIMITED
    Inventor: Kazuichi Oe
  • Patent number: 10725710
    Abstract: The hierarchical storage device includes: a collecting unit collecting access information related to each unit area included in a first storage device; a first specifying unit specifying a movement target area in the first storage device using a first parameter based on the access information collected by the collecting unit; a second specifying unit specifying a movement target area candidate in the first storage device using each parameter based on the access information; a counting unit counting a number of occurrences of data accesses to the movement target area candidate specified per parameter by the second specifying unit, based on the access information; and an updating unit determining as a recommended parameter the parameter whose number of occurrences of data accesses counted by the counting unit is the largest, and updating the first parameter used by the first specifying unit using the recommended parameter, and can efficiently exhibit device performance.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: July 28, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Kazuichi Oe
  • Publication number: 20200089425
    Abstract: An apparatus includes a queue that stores an instruction instructing a migration process between a first storing device and a second storing device having lower speed; and a processor configured to determine target data for the migration process, store an instruction for the target data into the queue, remove, from the queue, prior to storing of an instruction for first target data determined at a first timing, a second instruction as a removing target, the second instruction instructing migration from the second to first storing device and being determined at a second timing before the first timing, read an instruction from the queue, and control execution of the migration process according to the instruction read from the queue. Target data for an instruction instructing migration from the second to first storing device is data undergoing access concentration in the first storing device or data predicted to undergo access concentration.
    Type: Application
    Filed: August 15, 2019
    Publication date: March 19, 2020
    Applicant: FUJITSU LIMITED
    Inventor: Kazuichi Oe
  • Patent number: 10481829
    Abstract: An IO access concentration is precisely predicted by comparing first concentration state tendency information and second concentration state tendency information indicating a tendency of a concentration state of a unit region being in the concentration state, the first concentration state tendency information being collected during a first time period, the second concentration state tendency information being collected during a second time period prior to the first time period, and when the first concentration state tendency information is detected to vary by a standard value or more from the second concentration state tendency information, regenerating a data access prediction information by excluding a data access history collected during the second time period.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: November 19, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Kazuichi Oe
  • Publication number: 20190324677
    Abstract: A method for data migration between a first storage device and a second storage device whose performance is different from that of the first storage device, the method includes: executing comparison processing that includes comparing a first projected effect in a case of migrating data in an access concentration area of the second storage device to the first storage device and a second projected effect in a case of storing in the first storage device a copy of data in the second storage device and using the copy of data as cached data without migrating the data, and executing determination processing that includes determining to migrate data in a first area of the second storage device to the first storage device when the first projected effect is greater than the second projected effect, the first area being the access concentration area of the second storage device.
    Type: Application
    Filed: April 11, 2019
    Publication date: October 24, 2019
    Applicant: FUJITSU LIMITED
    Inventor: Kazuichi Oe
  • Patent number: 10168944
    Abstract: An information processing apparatus controlling moving of data stored in a first storage region selected from a plurality of storage regions of a first storage device to a second storage device, the apparatus is configured to execute a collection of logs of accesses, specify the first storage region as an access concentration region based on the logs, move first data stored in the first storage region to the second storage device, specify a transition speed of the access concentration region, specify a first time period until the number of the accesses to the first storage region becomes the first number, at a first time, execute a prediction procedure predicting that the number of accesses to a second region becomes equal to or greater than the first number at a second time after the first time, based on the transition speed and the first time period.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: January 1, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Kazuichi Oe
  • Publication number: 20180267737
    Abstract: An apparatus monitors an access load state of a plurality of logical volumes of a first storage device, and determines that an access load state of a subset of the plurality of logical volumes has changed from a high load state to a low load state. The apparatus migrates, when the subset of the plurality of logical volumes remains in a low load state after an elapsed setting time since the load state of the subset of the plurality of logical volumes changed from a high load state to a low load state, data stored in the subset of the plurality of logical volumes to a second storage device having an access rate lower than the first storage device.
    Type: Application
    Filed: March 14, 2018
    Publication date: September 20, 2018
    Applicant: FUJITSU LIMITED
    Inventor: Kazuichi Oe
  • Publication number: 20180181307
    Abstract: An information processing device includes a first memory, a second memory and a processor coupled to the first memory and the second memory, the processor being configured to obtain access information about a number of times of data accesses including write accesses and read accesses, the data accesses being made to the first memory from another information processing device, perform processing of migration of data between the first memory and the second memory, and stop execution of the processing of the migration of the data from the second memory to the first memory when the number of times of data accesses per unit time is more than a first value and a ratio of the write accesses to the data accesses is less than a second value.
    Type: Application
    Filed: November 29, 2017
    Publication date: June 28, 2018
    Applicant: FUJITSU LIMITED
    Inventor: Kazuichi Oe
  • Publication number: 20180181343
    Abstract: An IO access concentration is precisely predicted by comparing first concentration state tendency information and second concentration state tendency information indicating a tendency of a concentration state of a unit region being in the concentration state, the first concentration state tendency information being collected during a first time period, the second concentration state tendency information being collected during a second time period prior to the first time period, and when the first concentration state tendency information is detected to vary by a standard value or more from the second concentration state tendency information, regenerating a data access prediction information by excluding a data access history collected during the second time period.
    Type: Application
    Filed: November 30, 2017
    Publication date: June 28, 2018
    Applicant: FUJITSU LIMITED
    Inventor: Kazuichi Oe
  • Patent number: 10007437
    Abstract: A management apparatus includes a memory and a processor coupled to the memory. The processor is configured to: sequentially read data from a movement-target storage area of a storage device included in a first storage apparatus when the data stored in the movement-target storage area is to be moved from the first storage apparatus to a second storage apparatus which is accessible at a higher speed than the first storage, the first storage apparatus including the storage device and a cache memory configured to cache the data stored in the storage device using a write-back scheme; read changed data among the pieces of data in the movement-target storage area from the cache memory; merge data read from the movement-target storage area and the changed data read from the cache memory; and write merged data to the second storage apparatus.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: June 26, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Kazuichi Oe
  • Patent number: 9823855
    Abstract: A storage control device controlling a storage system including a first storage device and a second storage device, the first storage device and the second storage device include a plurality of regions for storing data, respectively, a data transmission between the first storage device and the second storage device is executed by the region, the storage control device includes a memory, and a processor coupled to the memory and configured to determine a first region of the first storage device as a first transmitting target region, the first region having a first size, transmit, from the first storage device to the second storage device, second data having a second size smaller than the first size, and based on a response performance of the storage system during the transmitting of the second data, transmit first data stored in the first region from the first storage device to the second storage device.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: November 21, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Kazuichi Oe
  • Patent number: 9817583
    Abstract: An information processing device includes a processor. The processor is configured to allocate a plurality of allocation unit areas to a virtual volume from a first storage device and a second storage device. The processor is configured to generate evaluation information related to access for each of a plurality of divided areas into which each of the plurality of allocation unit areas is divided. The processor is configured to determine based on the generated evaluation information, when allocation to the virtual volume is changed from a first allocation unit area of the first storage device to a second allocation unit area of the second storage device, a first data transfer order of transferring data in divided area units from the first allocation unit area to the second allocation unit area. The processor is configured to transfer the data in accordance with the first data transfer order.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: November 14, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Kazutaka Ogihara, Kazuichi Oe, Motoyuki Kawaba
  • Patent number: 9804780
    Abstract: A storage apparatus is provided, including a first storage device; a second storage device having an access speed higher than an access speed of the first storage device; a monitor that monitors a write access load for the first storage device; a comparator that compares the write access load for the first storage device monitored by the monitor, with a load threshold; and a switch that causes write access target data to be written into the first and second storage devices, when it is determined by the comparator that the write access load for the first storage device does not exceed the load threshold, while causing the write access target data to be written into the first storage device, when it is determined by the comparator that the write access load for the first storage device exceeds the load threshold.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: October 31, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Kazuichi Oe, Motoyuki Kawaba
  • Patent number: 9720600
    Abstract: An apparatus is connected to a first storage and a second storage which is accessed at an access speed lower than an access speed of the first storage. The apparatus accesses each of blocks stored in the second storage, and counts, for each of the blocks, the number of accesses made for the each block. The apparatus determines, based on the number of accesses that has been counted for each of the blocks, a transfer target block that is a target which is to be transferred from the second storage to the first storage, and determines a transfer time at which transfer of the transfer target block is to be performed. The apparatus transfers the determined transfer target block to the first storage at the determined transfer time.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: August 1, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Motoyuki Kawaba, Kazuichi Oe, Kazutaka Ogihara
  • Publication number: 20170153845
    Abstract: An information processing apparatus controlling moving of data stored in a first storage region selected from a plurality of storage regions of a first storage device to a second storage device, the apparatus is configured to execute a collection of logs of accesses, specify the first storage region as an access concentration region based on the logs, move first data stored in the first storage region to the second storage device, specify a transition speed of the access concentration region, specify a first time period until the number of the accesses to the first storage region becomes the first number, at a first time, execute a prediction procedure predicting that the number of accesses to a second region becomes equal to or greater than the first number at a second time after the first time, based on the transition speed and the first time period.
    Type: Application
    Filed: November 7, 2016
    Publication date: June 1, 2017
    Applicant: FUJITSU LIMITED
    Inventor: Kazuichi Oe
  • Publication number: 20170123720
    Abstract: A storage device includes first and second memories and a processor. The processor is configured to calculate a second number of access times with respect to each of the first and second memories on basis of a first busy rate and a first number of access times with respect to each of the first and second memories at a predetermined timing. The first number of access times represents a number of access times per unit time. The second number of access times represents a maximum value of the number of access times per unit time. The processor is configured to estimate a third number of access times on basis of the first busy rate and the second number of access times of each of the first and second memories. The third number of access times represents a number of access times per unit time with respect to the storage device.
    Type: Application
    Filed: October 26, 2016
    Publication date: May 4, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Kazuichi Oe, TOSHIHARU MAKIDA, KIYOSHI SUGIOKA, Takeo Honda