Patents by Inventor Kazuki ISOZUMI

Kazuki ISOZUMI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240292627
    Abstract: A memory device includes at least one alternating stack of insulating layers and electrically conductive layers overlying a source layer, a memory opening vertically extending through the at least one alternating stack, and a memory opening fill structure located in the memory opening and containing a vertical stack of memory elements and a vertical semiconductor channel. The memory opening fill structure includes a lateral protrusion having a tapered sidewall surface such that a lateral extent of the lateral protrusion decreases with a vertical distance from the source layer. One of the electrically conductive layers of the at least one alternating stack is a taper-containing electrically conductive layer that is located at a level of the lateral protrusion of the memory opening fill structure.
    Type: Application
    Filed: May 9, 2024
    Publication date: August 29, 2024
    Inventors: Takuya MUROOKA, Peng ZHANG, Kazuki ISOZUMI, Shinsuke YADA, Motoo OHAGA, Satoshi SHIMIZU
  • Publication number: 20240179906
    Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located in the memory openings and including a respective vertical semiconductor channel and a respective vertical stack of memory cells. An integrated line-and-via structure is provided, which is a unitary structure including a metallic plate portion that is a portion of or laterally contacts an electrically conductive layer, and a metallic via portion that vertically extends through dielectric material plates that overlie the metallic plate portion.
    Type: Application
    Filed: July 14, 2023
    Publication date: May 30, 2024
    Inventors: Naohiro HOSODA, Kazuki ISOZUMI, Takayuki MAEKURA, Hiroyuki OGAWA, Koichi MATSUNO
  • Publication number: 20240179908
    Abstract: A memory device includes a first-tier alternating stack of first insulating layers and first electrically conductive layers, a source layer overlying the first-tier alternating stack, a second-tier alternating stack of second insulating layers and second electrically conductive layers overlying the source layer, a memory opening vertically extending through the first-tier alternating stack, the source layer, and the second-tier alternating stack, and a memory opening fill structure located in the memory opening. The memory opening fill structure includes a vertical semiconductor channel that extends through the first-tier alternating stack, the source layer, and the second-tier alternating stack. The vertical semiconductor channel has sidewall in contact with the source layer.
    Type: Application
    Filed: July 17, 2023
    Publication date: May 30, 2024
    Inventors: Naohiro HOSODA, Kazuki ISOZUMI, Masanori TSUTSUMI
  • Publication number: 20240064985
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. The electrically conductive layers include word-line-level electrically conductive layers and drain-select-level electrically conductive layers overlying the word-line-level electrically conductive layers. An array of memory opening fill structures is located within an array of memory openings vertically extending through the alternating stack. An encapsulated cavity vertically extends through the drain-select-level electrically conductive layers. The array of memory opening fill structures includes two rows of first memory opening fill structures that are arranged along a first horizontal direction. Each of the first memory opening fill structures includes a respective planar straight sidewall in contact with a respective portion of a pair of straight sidewalls of the encapsulated cavity.
    Type: Application
    Filed: November 2, 2023
    Publication date: February 22, 2024
    Inventors: Masanori Tsutsumi, Kazuki Isozumi, Peng Zhang
  • Patent number: 11894298
    Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures contains a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a crystalline blocking dielectric metal oxide layer, and a metal oxide amorphous dielectric nucleation layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the crystalline blocking dielectric metal oxide layers and each of the electrically conductive layers.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: February 6, 2024
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Masanori Tsutsumi, Naohiro Hosoda, Shuichi Hamaguchi, Kazuki Isozumi, Genta Mizuno, Yusuke Mukae, Ryo Nakamura, Yu Ueda
  • Patent number: 11776628
    Abstract: The following disclosure is directed to mitigating issues related to semi-circle drain side select gate (SC-SGD) memory holes in memory structures. When a memory hole is cut, the channel and the charge trap layer of the memory hole cut. Further, the outer dielectric layer (used to shield the channel and the charge trap layer) is cut and partially removed. When the selected SC-SGD is selected for an operation (e.g., programming), the channel and the charge trap layer are exposed to neighboring electrical field from bias voltage applied to an unselected SC-SGD. To prevent or mitigate the effects of this electrical field, a negative bias voltage is applied to the unselected SC-SGD. Additionally, this disclosure is directed to self-compensating techniques for SC-SGD. For example, the memory structure can utilize the neighboring electric field during verify, program, and read operations, whether the neighboring electric field is relatively strong or weak.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: October 3, 2023
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Kazuki Isozumi, Parth Amin
  • Patent number: 11758718
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, first memory opening fill structures extending through the alternating stack and including a respective first vertical semiconductor channel having a tubular section and a semi-tubular section, second memory opening fill structures, first bit lines electrically connected to a respective subset of the first drain regions, second bit lines electrically connected to a respective subset of the second drain regions, and an erase voltage application circuit configured to electrically bias the first bit lines at a first bit line erase voltage and the second bit lines at a second bit line erase voltage during an erase operation. The first bit line erase voltage is greater than the second bit line erase voltage.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: September 12, 2023
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yu-Chung Lien, Abhijith Prakash, Keyur Payak, Jiahui Yuan, Huai-Yuan Tseng, Shinsuke Yada, Kazuki Isozumi
  • Patent number: 11581049
    Abstract: Apparatus and methods are described to reduce program disturb for a memory string with a partial select gate drain, which is partially cut by a shallow trench. The memory string with a partial select gate drain is linked with a neighboring full select gate drain that during its programming can cause a program disturb in the memory string with a partial select gate drain. The bias voltage applied to the selected full select gate drain can be controlled from a high state for low memory program states to a lower state for the high memory program states. The high data states may cause program disturb. The reduction in the bias voltage can match a reduction in the bias voltage applied to the bit lines to reduce the program disturb while providing adequate signal to program the high states on the memory string of the full select gate drain.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: February 14, 2023
    Assignee: SanDisk Technologies LLC
    Inventors: Kazuki Isozumi, Parth Amin, Sayako Nagamine, Anubhav Khandelwal
  • Publication number: 20230016518
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, first memory opening fill structures extending through the alternating stack and including a respective first vertical semiconductor channel having a tubular section and a semi-tubular section, second memory opening fill structures, first bit lines electrically connected to a respective subset of the first drain regions, second bit lines electrically connected to a respective subset of the second drain regions, and an erase voltage application circuit configured to electrically bias the first bit lines at a first bit line erase voltage and the second bit lines at a second bit line erase voltage during an erase operation. The first bit line erase voltage is greater than the second bit line erase voltage.
    Type: Application
    Filed: July 14, 2021
    Publication date: January 19, 2023
    Inventors: Yu-Chung LIEN, Abhijith PRAKASH, Keyur PAYAK, Jiahui YUAN, Huai-Yuan TSENG, Shinsuke YADA, Kazuki ISOZUMI
  • Publication number: 20220406378
    Abstract: The following disclosure is directed to mitigating issues related to semi-circle drain side select gate (SC-SGD) memory holes in memory structures. When a memory hole is cut, the channel and the charge trap layer of the memory hole cut. Further, the outer dielectric layer (used to shield the channel and the charge trap layer) is cut and partially removed. When the selected SC-SGD is selected for an operation (e.g., programming), the channel and the charge trap layer are exposed to neighboring electrical field from bias voltage applied to an unselected SC-SGD. To prevent or mitigate the effects of this electrical field, a negative bias voltage is applied to the unselected SC-SGD. Additionally, this disclosure is directed to self-compensating techniques for SC-SGD. For example, the memory structure can utilize the neighboring electric field during verify, program, and read operations, whether the neighboring electric field is relatively strong or weak.
    Type: Application
    Filed: June 17, 2021
    Publication date: December 22, 2022
    Applicant: SanDisk Technologies LLC
    Inventors: Xiang Yang, Kazuki Isozumi, Parth Amin
  • Publication number: 20220383967
    Abstract: Apparatus and methods are described to reduce program disturb for a memory string with a partial select gate drain, which is partially cut by a shallow trench. The memory string with a partial select gate drain is linked with a neighboring full select gate drain that during its programming can casuse a program disturb in the memory string with a partial select gate drain. The bias voltage applied to the selected full select gate drain can be controlled from a high state for low memory program states to a lower state for the high memory program states. The high data states may cause program disturb. The reduction in the bias voltage can match a reduction in the bias voltage applied to the bit lines to reduce the program disturb while providing adequate signal to program the high states on the memory string of the full select gate drain.
    Type: Application
    Filed: June 1, 2021
    Publication date: December 1, 2022
    Applicant: SanDisk Technologies LLC
    Inventors: Kazuki Isozumi, Parth Amin, Sayako Nagamine, Anubhav Khandelwal
  • Publication number: 20220216145
    Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures contains a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a crystalline blocking dielectric metal oxide layer, and a metal oxide amorphous dielectric nucleation layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the crystalline blocking dielectric metal oxide layers and each of the electrically conductive layers.
    Type: Application
    Filed: March 22, 2022
    Publication date: July 7, 2022
    Inventors: Masanori TSUTSUMI, Naohiro HOSODA, Shuichi HAMAGUCHI, Kazuki ISOZUMI, Genta MIZUNO, Yusuke MUKAE, Ryo NAKAMURA, Yu UEDA
  • Patent number: 11289416
    Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures contains a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a crystalline blocking dielectric metal oxide layer, and a metal oxide amorphous dielectric nucleation layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the crystalline blocking dielectric metal oxide layers and each of the electrically conductive layers.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: March 29, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Masanori Tsutsumi, Naohiro Hosoda, Shuichi Hamaguchi, Kazuki Isozumi, Genta Mizuno, Yusuke Mukae, Ryo Nakamura, Yu Ueda
  • Publication number: 20210159167
    Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures contains a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a crystalline blocking dielectric metal oxide layer, and a metal oxide amorphous dielectric nucleation layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the crystalline blocking dielectric metal oxide layers and each of the electrically conductive layers.
    Type: Application
    Filed: November 26, 2019
    Publication date: May 27, 2021
    Inventors: Masanori TSUTSUMI, Naohiro HOSODA, Shuichi HAMAGUCHI, Kazuki ISOZUMI, Genta MIZUNO, Yusuke MUKAE, Ryo NAKAMURA, Yu Yu UEDA