Patents by Inventor Kazuki Matsue

Kazuki Matsue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7180794
    Abstract: In a ring oscillator constituting an oscillating circuit, resistor circuits are used as delay circuits to be connected to respective inverters. That is, the inverters and the resistors are connected in series so that the resistor is provided between the adjacent inverters. With the arrangement, it is possible to provide an oscillating circuit which is less dependent on any of power supply voltages, temperatures, and manufacturing variations, while maintaining a characteristic in which the oscillating frequency decreases as an output voltage of a booster circuit increases.
    Type: Grant
    Filed: November 29, 2002
    Date of Patent: February 20, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Kazuki Matsue
  • Patent number: 7050333
    Abstract: An object of the present invention is to provide a nonvolatile semiconductor memory device having a storage region constructed by a plurality of electrically rewritable nonvolatile memory cells and a booster circuit for boosting a power source voltage to thereby generate a voltage necessary to rewrite the storage region, wherein the power source voltage can be prevented from being decreased in the device and data in the storage region can be stably rewritten. The nonvolatile semiconductor memory device has a voltage determining part for determining a voltage level of a predetermined node in the semiconductor memory device in rewriting of the storage region, and a rewrite unit determining part for determining the number of bits of input data to be rewritten at once on the basis of a result of determination of the voltage determining part.
    Type: Grant
    Filed: April 22, 2004
    Date of Patent: May 23, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Kazuki Matsue
  • Publication number: 20050063231
    Abstract: In a ring oscillator constituting an oscillating circuit, resistor circuits are used as delay circuits to be connected to respective inverters. That is, the inverters and the resistors are connected in series so that the resistor is provided between the adjacent inverters. With the arrangement, it is possible to provide an oscillating circuit which is less dependent on any of power supply voltages, temperatures, and manufacturing variations, while maintaining a characteristic in which the oscillating frequency decreases as an output voltage of a booster circuit increases.
    Type: Application
    Filed: November 29, 2002
    Publication date: March 24, 2005
    Inventor: Kazuki Matsue
  • Publication number: 20040213068
    Abstract: An object of the present invention is to provide a nonvolatile semiconductor memory device having a storage region constructed by a plurality of electrically rewritable nonvolatile memory cells and a booster circuit for boosting a power source voltage to thereby generate a voltage necessary to rewrite the storage region, wherein the power source voltage can be prevented from being decreased in the device and data in the storage region can be stably rewritten. The nonvolatile semiconductor memory device has a voltage determining part for determining a voltage level of a predetermined node in the semiconductor memory device in rewriting of the storage region, and a rewrite unit determining part for determining the number of bits of input data to be rewritten at once on the basis of a result of determination of the voltage determining part.
    Type: Application
    Filed: April 22, 2004
    Publication date: October 28, 2004
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Kazuki Matsue
  • Patent number: 5771191
    Abstract: A method for inspecting a semiconductor memory device by using an inspection microcomputer and a memory for storing a test program for the inspection. The semiconductor memory device includes a non-volatile memory area, a peripheral circuit thereof, a control circuit for controlling writing and erasing of data to and from the non-volatile memory area via the peripheral circuit, and a control bus for connecting the control circuit and the peripheral circuit. The method includes the steps of: deactivating the control circuit; connecting the inspection microcomputer and the memory to the control bus; and inspecting the peripheral circuit and the non-volatile memory area by the inspection microcomputer.
    Type: Grant
    Filed: April 23, 1997
    Date of Patent: June 23, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Kazuki Matsue