Patents by Inventor Kazuki MINAMIKAWA

Kazuki MINAMIKAWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240321871
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the second conductivity type, and a second electrode. The third semiconductor region is located on the second semiconductor region, and has a higher second-conductivity-type impurity concentration than the second semiconductor region. The second electrode is located on the third semiconductor region. The second electrode includes a first part and a second part. The first part is located in the second semiconductor region. The second part is positioned on the first part, and contacts the third semiconductor region in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region. A length of the first part is greater than a length of the second part in the second direction.
    Type: Application
    Filed: September 7, 2023
    Publication date: September 26, 2024
    Inventors: Kazuki MINAMIKAWA, Daiki YOSHIKAWA, Kazutoshi NAKAMURA
  • Publication number: 20230307509
    Abstract: A semiconductor device includes first and second electrodes, a semiconductor part, a structure body, and an insulating part. The semiconductor part includes first to fifth semiconductor regions. The structure body includes a gate part and a dummy part. The gate part includes at least one gate electrode. The dummy part includes at least two dummy electrodes. The gate part and the dummy part are alternately arranged. The insulating part is located between the gate electrode and the semiconductor part. The gate part is located in the fourth semiconductor region. A first potential is applied to the second electrode. A second potential that is greater than the first potential is applied to the gate electrode. A third potential that is greater than the first potential is applied to the dummy electrode located at a position next to the gate part.
    Type: Application
    Filed: September 7, 2022
    Publication date: September 28, 2023
    Inventors: Kazuki Minamikawa, Daiki Yoshikawa, Norio Yasuhara, Kazutoshi Nakamura
  • Publication number: 20230299186
    Abstract: A semiconductor chip includes a semiconductor substrate, a plurality of first wirings extending in a first direction parallel to the upper surface of the semiconductor substrate and disposed entirely above the upper surface of the semiconductor substrate, a second wiring disposed between two of the first wirings that are adjacent to each other and entirely below the upper surface of the semiconductor substrate such that an upper surface of the second wiring is below a lower surface of the two first wirings, and a first insulating film provided on the second wiring and spaced apart from the two first wirings in a second direction that is perpendicular to the first direction, the first insulating film having an upper surface that is above the lower surface of the two first wirings.
    Type: Application
    Filed: September 2, 2022
    Publication date: September 21, 2023
    Inventor: Kazuki MINAMIKAWA
  • Patent number: 11056557
    Abstract: A semiconductor device includes a semiconductor layer on a first electrode. The semiconductor layer includes a first region of a first type, a second region of a second type, a third region of the second type, and a fourth region of the first type. The second region is above the first region. The third region surrounds the second region. The fourth region surrounds the third region. The second electrode includes a first portion above the second region and a second portion surrounding the first portion. The third electrode surrounds the second electrode and is electrically connected to the fourth region. The semi-insulating layer is electrically connected to the second electrode and the third electrode. A first end portion of the first insulating layer is above the third region.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: July 6, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Kazuki Minamikawa, Yukie Nishikawa, Kotaro Zaima
  • Publication number: 20200295128
    Abstract: A semiconductor device includes a semiconductor layer on a first electrode. The semiconductor layer includes a first region of a first type, a second region of a second type, a third region of the second type, and a fourth region of the first type. The second region is above the first region. The third region surrounds the second region. The fourth region surrounds the third region. The second electrode includes a first portion above the second region and a second portion surrounding the first portion. The third electrode surrounds the second electrode and is electrically connected to the fourth region. The semi-insulating layer is electrically connected to the second electrode and the third electrode. A first end portion of the first insulating layer is above the third region.
    Type: Application
    Filed: August 27, 2019
    Publication date: September 17, 2020
    Inventors: Kazuki MINAMIKAWA, Yukie NISHIKAWA, Kotaro ZAIMA