Abstract: A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including a plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single port memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.

Abstract: A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including a plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single port memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.

Abstract: A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including 8 plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single port memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.

Abstract: The television receiver including a display device capable of displaying a video signal having a predetermined display former of this invention includes; a plurality of video signal sources; a selection circuit for selecting one of a plurality of video signals output from the plurality of video signal sources; and an image processor for converting a format of the video signal selected by the selection circuit into the predetermined display format, wherein a video signal output from the processor is supplied to the display device.

Abstract: A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including a plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single part memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.

Abstract: According to the signal processing method of the invention, control data is previously generated by using the name of a control signal included in an object signal, and then, the object signal including the control signal is input. The name of the control signal in the control data is substituted with the content of the control signal included in the object signal, and then the object signal is processed by a signal processing unit by using the control data including the content of the control signal. Therefore, the signal processing unit can change the processing to be performed on the object signal in accordance with the content of the control signal included in the object signal.

Abstract: A plurality of processing elements are connected in cascade so as to constitute a single signal processing apparatus. The signal processing apparatus has a first path for transferring an input data signal and a second path for transferring a processing result of the input data signal.

Abstract: A plurality of signal processing elements are cascade-connected to form a signal processor having three signal paths. The signal processor is a small-sized device which can be shared by sum-of-products calculation and division. In each signal processing element, first and second shifters and an adder-subtracter are used for performing shift addition for multiplication of a variable by a constant which is a basis of the sum-of-products calculation. The adder-subtracter and a third shifter for shifting a result obtained by the adder-subtracter are used for performing subtraction and shifting for obtaining a partial quotient and a partial remainder of division. The partial quotient thus obtained is transferred to the signal processing element in the next stage through a flag holding circuit.

Abstract: In order to establish connections of plural arithmetic units capable of performing basic functions such as filtering in various connection ways, a bus switch is provided which has a plurality of input data lines connected with output terminals of the arithmetic units, at least one external input data line, a plurality of output data lines connected with input terminals of the arithmetic units, and at least one external output data line. In addition, two register sets are provided which hold arithmetic control information designating contents of processes to be performed by the arithmetic units and connection control information designating connection ways within the bus switch. Depending on the broadcasting system, information held by one of the register sets and information held by the other are updated, and, according to a process algorithm, either one of the two register sets is selected.

Abstract: A coprocessor is incorporated in a processor comprising a CPU, an instruction cache, a data memory, a bus controller, an interruption control section and a DMA controller. This coprocessor has a parallel sum-of-products arithmetic operation section, a comparator, an I/O register section, and a sum-of-products factor register section. A frame memory, provided on the input side, stores MUSE or NTSC signals digitized per pixel. The DMA is in control of the transfer of data between the input-side frame memory and the data memory as well as the transfer of data between a frame memory provided on the output side and the data memory. Pixel data stored in the data memory is processed according to broadcasting systems by the switching of sum-of-products factors on the basis of software.

Abstract: A coprocessor is incorporated in a processor comprising a CPU, an instruction cache, a data memory, a bus controller, an interruption control section and a DMA controller. This coprocessor has a parallel sum-of-products arithmetic operation section, a comparator, an I/O register section, and a sum-of-products factor register section. A frame memory, provided on the input side, stores MUSE or NTSC signals digitized per pixel. The DMA is in control of the transfer of data between the input-side frame memory and the data memory as well as the transfer of data between a frame memory provided on the output side and the data memory. Pixel data stored in the data memory is processed according to broadcasting systems by the switching of sum-of-products factors on the basis of software.

Abstract: In order to establish connections of plural arithmetic units capable of performing basic functions such as filtering in various connection ways, a bus switch is provided which has a plurality of input data lines connected with output terminals of the arithmetic units, at least one external input data line, a plurality of output data lines connected with input terminals of the arithmetic units, and at least one external output data line. In addition, two register sets are provided which hold arithmetic control information designating contents of processes to be performed by the arithmetic units and connection control information designating connection ways within the bus switch. Depending on the broadcasting system, information held by one of the register sets and information held by the other are updated, and, according to a process algorithm, either one of the two register sets is selected.

Abstract: An improved signal processor is disclosed which is suitable for convergence processing of images that achieves parallel processing with a smaller bus structure. An arithmetic array is provided which is formed of ten arithmetic cells capable of concurrently operating. Each arithmetic cell is specified by a denotation of E?(column number),y(row number)! where the column number x is 1.ltoreq.x.ltoreq.4 and the row number y is x.ltoreq.y.ltoreq.4. Each arithmetic cell has a multiplier and an adder for multiply-add operation. An arithmetic cell, specified by E?x,y! where 2.ltoreq.x.ltoreq.4 and x.ltoreq.y.ltoreq.4, receives data from an E?x-1,y! arithmetic cell via a direct bus as well as from an E?x-1,y-1! arithmetic cell via an oblique bus. For example, when pixel data items as to four pixels horizontally arranged in an image are fed to the four arithmetic cells in the first column, the arithmetic cell in the fourth column provides a 4-tap horizontal filter operation result.

Abstract: A memory unit includes a plurality of read bit lines, a plurality of read word lines, a plurality of write bit lines, and a plurality of write word lines. An array of memory cells are connected to the read bit lines, the read word lines, the write bit lines, and the write word lines. Each of the memory cells includes at least two input sections, at least two output sections, and a memory element. The output sections are connected to at least two of the read word lines, respectively, and output data from the memory element to one of the read bit lines in response to signals on the read word lines. The input sections are connected to at least two of the write word lines, respectively, and output data from one of the write bit lines into the memory element in response to signals on the write word lines. A plurality of decoders connected to the read word lines decode a read address signal into output signals, respectively, which are fed to the read word lines.

Abstract: This invention discloses an improved signal processor comprising first to third arithmetic units forming a pipeline structure, first to third control information hold circuits each of which holds control information for its corresponding arithmetic unit, first to third selection circuits, and first to third signal transfer circuits. Transfer of a selection signal is delayed by a proportional interval of time to the processing time of each arithmetic unit. In order to perform the switching of arithmetical operations in each arithmetic unit according to the data flow in the pipeline processing, each selection circuit selects among the control information hold circuits depending on the selection signal transferred and provides control information held in a selected control information hold circuit to a corresponding arithmetic unit.

Abstract: A coprocessor is incorporated in a processor comprising a CPU, an instruction cache, a data memory, a bus controller, an interruption control section and a DMA controller. This coprocessor has a parallel sum-of-products arithmetic operation section, a comparator, an I/O register section, and a sum-of-products factor register section. A frame memory, provided on the input side, stores MUSE or NTSC signals digitized per pixel. The DMA is in control of the transfer of data between the input-side frame memory and the data memory as well as the transfer of data between a frame memory provided on the output side and the data memory. Pixel data stored in the data memory is processed according to broadcasting systems by the switching of sum-of-products factors on the basis of software.

Abstract: A memory unit includes a plurality of read bit lines, a plurality of read word lines, a plurality of write bit lines, and a plurality of write word lines. An array of memory cells are connected to the read bit lines, the read word lines, the write bit lines, and the write word lines. Each of the memory cells includes at least two input sections, at least two output sections, and a memory element. The output sections are connected to at least two of the read word lines, respectively, and output data from the memory element to one of the read bit lines in response to signals on the read word lines. The input sections are connected to at least two of the write word lines, respectively, and output data from one of the write bit lines into the memory element in response to signals on the write word lines. A plurality of decoders connected to the read word lines decode a read address signal into output signals, respectively, which are fed to the read word lines.

Abstract: A memory unit includes an array of memory cells. Word lines are connected to the memory cells. Bit lines are connected to the memory cells. A decoder receives an address signal at a timing which follows an occurrence of a clock signal by a given time t1. The address signal is in synchronism with the clock signal. The clock signal has a preset period t0. The decoder decodes the address signal into a word signal and outputs the word signal at a timing which follows the reception of the address signal by a given time t2. A delay device delays the clock signal by a preset time "t" and thereby converts the clock signal into a control signal. An access to a word of the memory cells is performed via one of the word lines in accordance with the word signal at a timing determined by the control signal. The bit lines are precharged at a timing determined by the control signal. The preset time "t" is longer than a sum of the times t1 and t2 but shorter than a half of the period t0.

Abstract: A memory unit includes an array of memory cells. Word lines are connected to the memory cells. Bit lines are connected to the memory cells. A decoder receives an address signal at a timing which follows an occurrence of a clock signal by a given time t1. The address signal is in synchronism with the clock signal. The clock signal has a preset period t0. The decoder decodes the address signal into a word signal and outputs the word signal at a timing which follows the reception of the address signal by a given time t2. A delay device delays the clock signal by a preset time "t" and thereby converts the clock signal into a control signal. An access to a word of the memory cells is performed via one of the word lines in accordance with the word signal at a timing determined by the control signal. The bit lines are precharged at a timing determined by the control signal. The preset time "t" is longer than a sum of the time t1 and t2 but shorter than a half of the period t0.