Abstract: Provided are an epoxy resin curing agent containing an amine composition or a modified product thereof, wherein the amine composition contains bis(aminomethyl)cyclohexane (A), a compound (B) represented by the specific formula (1), and a compound (C) represented by the specific formula (2), and wherein a mass ratio of the component (B) to the component (C) [(B)/(C)] is from 0.01 to 5.0, an epoxy resin composition, and use of an amine composition for an epoxy resin curing agent.

Abstract: Provided are an epoxy resin curing agent containing an amine composition or a modified product thereof, wherein the amine composition contains bis(aminomethyl)cyclohexane (A) and a compound (B) represented by the following formula (1), and wherein the content of the component (B) based on 100 parts by mass of the component (A) is from 1.5 to 20.0 parts by mass, an epoxy resin composition, and an epoxy resin curing agent for an amine composition. In the formula (1), R1 is an alkyl group having 1 to 6 carbon atoms optionally having a hydroxy group, R2NHCH2—, where R2 represents an alkyl group having 1 to 6 carbon atoms, or a group represented by the following formula (1A), and p is a number of 0 to 2. In the formula (1A), R3 represents a hydrogen atom or NH2—.

Abstract: A semiconductor memory (200) having a plurality of banks (10 and 20) of memory cells in which a parallel test operation can allow bits from each bank to be tested in parallel. According to one embodiment, the semiconductor memory may include a data amplifier (30) having a selection circuit (110), data sense circuit (120), data output circuit (130), control circuit (140), and comparator (C1). In a normal mode of operation, the selection circuit (110) may be coupled to receive I/O busses (IOAT/N and IOBT/N) from memory banks (10 and 20) and based on selection control signals (TR1 to TR4), may select data to be amplified by data sense circuit (120) and output to a read/write bus RWBST/N. In a test mode of operation, the selection circuit (110) may be coupled to receive I/O busses (IOAT/N and IOBT/N) from memory banks (10 and 20) and may couple data from each memory bank (10 and 20) to a data sense circuit (120) to be amplified and applied to comparator (C1).

Abstract: A reference voltage generating device and method enables dissipation current to be reduced at the time of normal operation. An oscillator outputs a voltage of a low level intermittently during a prescribed time interval. An operational amplifier operates only when an output voltage of the oscillator is a low level. When the output voltage of the oscillator is a high level, a reference voltage “VREF” becomes a floating state so that a level is maintained by compensating the capacity of a capacitor C1. The reference voltage “VREF,” whose electric charge leaks due to a leak at the junction of a transistor, is maintained while operating the operational amplifier during a time interval T in a time period 10 T.

Abstract: A semiconductor memory (200) having a plurality of banks (10 and 20) of memory cells in which a parallel test operation can allow bits from each bank to be tested in parallel. According to one embodiment, the semiconductor memory may include a data amplifier (30) having a selection circuit (110), data sense circuit (120), data output circuit (130), control circuit (140), and comparator (C1). In a normal mode of operation, the selection circuit (110) may be coupled to receive I/O busses (IOAT/N and IOBT/N) from memory banks (10 and 20) and based on selection control signals (TR1 to TR4), may select data to be amplified by data sense circuit (120) and output to a read/write bus RWBST/N. In a test mode of operation, the selection circuit (110) may be coupled to receive I/O busses (IOAT/N and IOBT/N) from memory banks (10 and 20) and may couple data from each memory bank (10 and 20) to a data sense circuit (120) to be amplified and applied to comparator (C1).

Abstract: A reference voltage generating circuit comprises a differential amplifier having a first input connected to receive a constant voltage and a second input connected through a voltage feedback path to an output of the differential amplifier so as to receive a voltage in proportion to an a first reference voltage outputted from the differential amplifier. A voltage divider composed of series-connected resistors is connected to the output of the differential amplifier so as to form a current path independent of the voltage feedback path, so that the voltage divider generates a second reference voltage different from the first reference voltage. Thus, a single reference voltage generating circuit generates a plurality of reference voltages.

Abstract: A semiconductor storage device (1100) having a burst mode capability for accomplishing a rapid read/write operation is disclosed. Included is a memory address generator circuit (100) having an address counter (102) which latches and increments the n least significant bits of a start address containing m bits, the address counter (102) producing a count value. An address latch (104) latches the m-n most significant bits of the start address, and an end address arithmetic circuit (106) produces a burst end address by subtracting 1 from the start address n least significant bits. A comparator circuit (108) generates a burst end signal (BSTEND) based on the comparison of the count value and the burst end address, the comparison being done by way of a generation of coincidence signals (k0-k2) by coincidence detector circuits included in the comparator circuit (108).

Abstract: The present invention provides a synchronous semiconductor memory device, from which data are read out, and to which the data are written after having been modified and corrected, which comprises a read data bus for transmitting said read data and a write data bus for transmitting said written data. In the memory device, the second read-modify-write (RMW) cycle can start during the first RMW cycle so that the memory device can decrease a RMW time in a continuous RMW operation and also speed up the RMW operation.

Abstract: In a method of write to a graphic memory where memory cells designated by a plurality of addresses selected simultaneously for one ROW address, the present method of write includes a first step of dividing the area corresponding to the column addresses designated by one row address of a memory cell array in to a plurality of segments each consisting of an arbitrary number of column addresses, a second step of designating a start address and an end address for each of the plurality of segments based on a first piece of information of column information, a third step of specifying the section designated by the start address and the end address as the candidate for the write object areas, and a fourth step of selecting segments having write object areas based on a second piece of information of the column address information, and writing specified data to the candidate for the write object areas of the segments having the write object areas.

Abstract: A semiconductor memory comprises a memory cell array having bit line pairs, a pair of I/O lines, column switches connected between the pair of I/O lines and an associated one of the bit line pairs, a timing signal generator generating a timing signal, an address latch circuit latching an address signal in response to the timing signal and a column decoder decoding the address signal latched into the address latch circuit to activate at least one of the column switches. The timing signal generator generates the timing signal synchronized with a clock signal during the normal write operation, and generates the timing signal having a lower frequency than the clock signal during the block-write operation.

Abstract: In a redundancy circuit, there is provided a data-transfer path switching circuit for switching on path-switching signals paths on which data is transferred from the data-storage places of the write shift register through the memory cell array to the data-storage place. Path switching signals are generated by blowing the fuse link corresponding to the number of data pieces input into the write shift register. The construction that the data to be read out first is transferred to the last data-storage place of the output circuit increases the speed of readout without shifting previously to readout when a shift register is used as output circuit. With a data register as output circuit, the output control circuit is fixed, thereby eliminating the need for trouble-some decoder switching.