Patents by Inventor Kazuki Ohya

Kazuki Ohya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Error-correcting code processing method and device
    Patent number: 9166624
    Abstract: An error-correcting code processing method includes: calculating descending symbols or ascending symbols or both, and calculating, as a parity, exclusive OR of all elements of an information symbol sequence; one or both of calculating exclusive OR for each element of the descending symbols, to generate low-order n bits of the descending symbols and calculating exclusive OR for each element of the ascending symbols, to generate low-order n bits of the ascending symbols; one or both of calculating exclusive OR of elements obtained by selecting, in descending order, elements from an element sequence resulting from arranging parities, to generate a high-order m bit of the descending symbols and calculating exclusive OR of elements obtained by selecting, in ascending order, elements from the element sequence, to generate a high-order m bit of the ascending symbols; and outputting the descending symbols or the ascending symbols or both as check symbols or a syndrome.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: October 20, 2015
    Assignee: OSAKA UNIVERSITY
    Inventors: Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Takashi Hamabe, Kazuki Ohya, Masaaki Abe
  • ERROR-CORRECTING CODE PROCESSING METHOD AND DEVICE
    Publication number: 20130061115
    Abstract: An error-correcting code processing method includes: calculating descending symbols or ascending symbols or both, and calculating, as a parity, exclusive OR of all elements of an information symbol sequence; one or both of calculating exclusive OR for each element of the descending symbols, to generate low-order n bits of the descending symbols and calculating exclusive OR for each element of the ascending symbols, to generate low-order n bits of the ascending symbols; one or both of calculating exclusive OR of elements obtained by selecting, in descending order, elements from an element sequence resulting from arranging parities, to generate a high-order m bit of the descending symbols and calculating exclusive OR of elements obtained by selecting, in ascending order, elements from the element sequence, to generate a high-order m bit of the ascending symbols; and outputting the descending symbols or the ascending symbols or both as check symbols or a syndrome.
    Type: Application
    Filed: May 11, 2011
    Publication date: March 7, 2013
    Inventors: Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Takashi Hamabe, Kazuki Ohya, Masaaki Abe