Patents by Inventor Kazuki Sawa

Kazuki Sawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11568812
    Abstract: A display device includes: a luminance converter which converts input gradation value into a corresponding target luminance value; a luminance correction calculator which calculates output gradation value from the target luminance value and calculates a corrected luminance value from the output gradation value, using an efficiency residual ratio which is an index representing the light-emitting element deterioration degree; a current stress calculator which converts current stress amount on the light-emitting element calculated from the corrected luminance value into current stress amount when reference current flows through the light-emitting element, and calculates the accumulated current stress amount; a temperature stress calculator which converts temperature stress amount on the light-emitting element under environmental temperature into temperature stress amount on the light-emitting element under reference temperature, and calculates the accumulated current stress amount; and an efficiency residual rat
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: January 31, 2023
    Assignee: JOLED INC.
    Inventors: Eiji Iwauchi, Kazuki Sawa, Kazuhiro Yoneda
  • Patent number: 11450278
    Abstract: A display device includes: a luminance converter which converts input gradation value into a corresponding target luminance value; a luminance correction calculator which calculates output gradation value from the target luminance value using efficiency residual ratio representing a deterioration degree of a light-emitting element, and calculates a corrected luminance value therefrom; a current stress calculator which converts current stress amount on a light-emitting element calculated from the corrected luminance value into current stress amount when first reference current flows through the light-emitting element, and accumulates this to calculate an accumulated first stress amount; a CB stress calculator which converts CB stress amount on the light-emitting element into current stress amount when second reference current flows through the light-emitting element, and accumulates this to calculate an accumulated second stress amount; and an efficiency residual ratio calculator which updates the efficiency r
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: September 20, 2022
    Assignee: JOLED INC.
    Inventors: Eiji Iwauchi, Kazuki Sawa, Kazuhiro Yoneda
  • Publication number: 20220076626
    Abstract: A display device includes: a luminance converter which converts input gradation value into a corresponding target luminance value; a luminance correction calculator which calculates output gradation value from the target luminance value using efficiency residual ratio representing a deterioration degree of a light-emitting element, and calculates a corrected luminance value therefrom; a current stress calculator which converts current stress amount on a light-emitting element calculated from the corrected luminance value into current stress amount when first reference current flows through the light-emitting element, and accumulates this to calculate an accumulated first stress amount; a CB stress calculator which converts CB stress amount on the light-emitting element into current stress amount when second reference current flows through the light-emitting element, and accumulates this to calculate an accumulated second stress amount; and an efficiency residual ratio calculator which updates the efficiency r
    Type: Application
    Filed: September 3, 2021
    Publication date: March 10, 2022
    Applicant: JOLED INC.
    Inventors: Eiji IWAUCHI, Kazuki SAWA, Kazuhiro YONEDA
  • Publication number: 20220068204
    Abstract: A display device includes: a luminance converter which converts input gradation value into a corresponding target luminance value; a luminance correction calculator which calculates output gradation value from the target luminance value and calculates a corrected luminance value from the output gradation value, using an efficiency residual ratio which is an index representing the light-emitting element deterioration degree; a current stress calculator which converts current stress amount on the light-emitting element calculated from the corrected luminance value into current stress amount when reference current flows through the light-emitting element, and calculates the accumulated current stress amount; a temperature stress calculator which converts temperature stress amount on the light-emitting element under environmental temperature into temperature stress amount on the light-emitting element under reference temperature, and calculates the accumulated current stress amount; and an efficiency residual rat
    Type: Application
    Filed: August 19, 2021
    Publication date: March 3, 2022
    Applicant: JOLED INC.
    Inventors: Eiji IWAUCHI, Kazuki SAWA, Kazuhiro YONEDA
  • Patent number: 10319296
    Abstract: A display device correction method performed by a control unit that performs display control on an organic electroluminescent (EL) panel including a plurality of display pixels, in an organic EL display which includes the organic EL panel and the control unit. The display device correction method includes: obtaining a cumulative value of a pixel signal supplied to a drive transistor which is included in a current pixel to be processed among the plurality of display pixels and supplies drive current according to the pixel signal to an organic EL element (OEL); calculating a shift amount of a threshold voltage of the drive transistor, using the cumulative value; calculating an amount of change in mobility, using the shift amount; and calculating a correction parameter for correcting a pixel signal, using the amount of change in mobility.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: June 11, 2019
    Assignee: JOLED INC.
    Inventors: Kazuki Sawa, Hiroshi Hayashi, Tomoyuki Maeda
  • Publication number: 20180076461
    Abstract: A method for forming an electrode for a lithium ion battery is disclosed. The method includes preparing a mixture slurry, coating the mixture slurry onto a current collector body, and heating the mixture slurry coating to form an active substance layer. The slurry mixture can be prepared by mixing a polyimide precursor solution and active substance particles. The polyimide resin in the active substance layer is porous due to the method.
    Type: Application
    Filed: November 15, 2017
    Publication date: March 15, 2018
    Inventors: Hiroshi YAMADA, Kazuki SAWA, Yoshihito NIMURA, Yuusuke EDA, Yasue OKUYAMA, Takuhiro MIYUKI, Tetsuo SAKAI
  • Publication number: 20170287397
    Abstract: A display device correction method performed by a control unit that performs display control on an organic electroluminescent (EL) panel including a plurality of display pixels, in an organic EL display which includes the organic EL panel and the control unit. The display device correction method includes: obtaining a cumulative value of a pixel signal supplied to a drive transistor which is included in a current pixel to be processed among the plurality of display pixels and supplies drive current according to the pixel signal to an organic EL element (OEL); calculating a shift amount of a threshold voltage of the drive transistor, using the cumulative value; calculating an amount of change in mobility, using the shift amount; and calculating a correction parameter for correcting a pixel signal, using the amount of change in mobility.
    Type: Application
    Filed: August 27, 2015
    Publication date: October 5, 2017
    Applicant: JOLED INC.
    Inventors: Kazuki SAWA, Hiroshi HAYASHI, Tomoyuki MAEDA
  • Publication number: 20140011089
    Abstract: The invention addresses the problem of providing a polyimide precursor, a polyimide precursor solution, and a mixture slurry, each capable of more firmly binding active material particles to a current collecting body. The polyimide precursor solution according to the invention contains a tetracarboxylic acid ester compound, a diamine compound having an anionic group, and a solvent. The solvent dissolves the tetracarboxylic acid ester compound and the diamine compound. As the tetracarboxylic acid ester compound, a 3,3?,4,4?-benzophenonetetracarboxylic acid diester is particularly preferred. Examples of the “diamine compound having an anionic group” include 3,4-diaminobenzoic acid, 3,5-diaminobenzoic acid, and m-phenylenediamine-4-sulfonic acid. Further, the mixture slurry according to the invention contains active material particles in the polyimide precursor solution.
    Type: Application
    Filed: March 26, 2012
    Publication date: January 9, 2014
    Applicants: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, I.S.T. CORPORATION
    Inventors: Hiroshi Yamada, Kazuki Sawa, Yoshihito Nimura, Yuusuke Eda, Yasue Okuyama, Takuhiro Miyuki, Tetsuo Sakai
  • Patent number: 8508555
    Abstract: A plasma display device includes an image signal processing circuit having a sequential addressing processing circuit, an alternate addressing processing circuit and an image data selection circuit. The sequential addressing processing circuit includes a sequential addressing array unit for converting an image signal into image data arranged in the order corresponding to a sequential address operation. The alternate addressing processing circuit includes an alternate addressing array unit for converting an image signal into image data arranged in the order corresponding to an alternate address operation. The image data selecting circuit selecting between the sequential and alternate addressing operations based on predicted power consumption.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: August 13, 2013
    Assignee: Panasonic Corporation
    Inventor: Kazuki Sawa
  • Publication number: 20130021318
    Abstract: In display of an image on a plasma display panel, the contrast of the display image is enhanced. For this purpose, the voltage obtained by subtracting the voltage applied to the data electrode from the low-side voltage of the sustain pulses applied to the scan electrode in the sustain period is defined as a first voltage. The voltage obtained by subtracting the voltage applied to the data electrode from the high-side voltage of the sustain pulses applied to the scan electrode is defined as a second voltage. The voltage obtained by subtracting the low-side voltage of the address pulse applied to the data electrode from the low-side voltage of the scan pulse applied to the scan electrode in the address period is defined as a third voltage.
    Type: Application
    Filed: May 27, 2011
    Publication date: January 24, 2013
    Applicant: PANASONIC CORPORATION
    Inventors: Yutaka Yoshihama, Kazuki Sawa
  • Patent number: 8300707
    Abstract: A frame correlation determination part is for determining a level of correlation of decoded image signals between frames. A flat region detection part is for detecting an image region in which a difference in brightness between neighboring pixels is small as a flat region from the decoded image signals. A high-frequency region detection part is for detecting an image region including a high spatial frequency component as a high-frequency region from the decoded image signal. A smoothing processing part is for performing smoothing processing to the decoded image signal corresponding to a predetermined region. A processing region setting part is for setting an image region in which the smoothing processing part is to perform smoothing processing to the decoded image signal are included. The processing region setting part sets at least a region in frames in which a correlation between frames is low and which is a flat region and not a high frequency region in the decoded image signals, as a processing region.
    Type: Grant
    Filed: October 14, 2005
    Date of Patent: October 30, 2012
    Assignee: Panasonic Corporation
    Inventor: Kazuki Sawa
  • Publication number: 20120242631
    Abstract: A loading phenomenon in a plasma display panel is reduced.
    Type: Application
    Filed: December 9, 2010
    Publication date: September 27, 2012
    Inventors: Kazuki Sawa, Tomoyuki Saito
  • Patent number: 8138995
    Abstract: A plasma display device includes the following elements: an image signal conversion circuit for converting an image signal into an image data; a data electrode driver circuit for driving data electrodes according to the image data; a power calculation circuit for calculating a power consumption of the data electrode driver circuit according to the image data; and a temperature calculation circuit for calculating a temperature of the data electrode driver circuit according to the image data. The image signal conversion circuit converts the image signal into an image data decreasing the power consumption of the data electrode driver circuit at least when the calculated power consumption exceeds a predetermined power threshold value, or when the calculated temperature exceeds a predetermined temperature threshold value.
    Type: Grant
    Filed: January 11, 2008
    Date of Patent: March 20, 2012
    Assignee: Panasonic Corporation
    Inventors: Takeru Yamashita, Kazuki Sawa, Hiroko Yamamoto
  • Publication number: 20100265276
    Abstract: A plasma display device includes an image signal processing circuit having a sequential addressing processing circuit and an alternate addressing processing circuit. The sequential addressing processing circuit includes a sequential addressing array unit for converting an image signal into image data arranged in the order corresponding to a sequential address operation, a first data power conversion unit for converting the image data converted from the received image signal into image data which allows to have low electric power consumption, and a first addressing stop unit for stopping an address operation in specific subfields. The alternate addressing processing circuit includes an alternate addressing array unit for converting an image signal into image data arranged in the order corresponding to an alternate address operation, a second data power conversion unit, and a second addressing stop unit. The number of the specific subfields is the same between the first and second data power conversion units.
    Type: Application
    Filed: January 30, 2009
    Publication date: October 21, 2010
    Applicant: Panasonic Corporation
    Inventor: Kazuki Sawa
  • Publication number: 20100033509
    Abstract: An image display device includes an error diffusion circuit for limiting the gradation level of an image signal to that displayable on the image display device, and diffusing error data produced by the limitation to neighboring pixels. The error diffusion circuit includes an error replacement unit for replacing the error data with fixed-value data in a predetermined period of the image signal.
    Type: Application
    Filed: February 29, 2008
    Publication date: February 11, 2010
    Applicant: Panasonic Corporation
    Inventor: Kazuki Sawa
  • Patent number: 7567299
    Abstract: A frame-cyclic noise reduction device of an image display device, in which one field is divided into a plurality of sub-fields, and turned-on sub-fields are properly combined to provide an image with gradation. The noise reduction device detects an area where an edge portion of an image becomes unclear, i.e., where sub-field fuzziness becomes worse, and controls a cyclic amount for the area in which sub-field fuzziness becomes worse so as to be different from that for another area, thereby decreasing noise.
    Type: Grant
    Filed: January 28, 2005
    Date of Patent: July 28, 2009
    Assignee: Panasonic Corporation
    Inventor: Kazuki Sawa
  • Publication number: 20090184953
    Abstract: A plasma display device includes the following elements: an image signal conversion circuit for converting an image signal into an image data; a data electrode driver circuit for driving data electrodes according to the image data; a power calculation circuit for calculating a power consumption of the data electrode driver circuit according to the image data; and a temperature calculation circuit for calculating a temperature of the data electrode driver circuit according to the image data. The image signal conversion circuit converts the image signal into an image data decreasing the power consumption of the data electrode driver circuit at least when the calculated power consumption exceeds a predetermined power threshold value, or when the calculated temperature exceeds a predetermined temperature threshold value.
    Type: Application
    Filed: January 11, 2008
    Publication date: July 23, 2009
    Inventors: Takeru Yamashita, Kazuki Sawa, Hiroko Yamamoto
  • Publication number: 20080252789
    Abstract: A frame correlation determination part is for determining a level of correlation of decoded image signals between frames. A flat region detection part is for detecting an image region in which a difference in brightness between neighboring pixels is small as a flat region from the decoded image signals. A high-frequency region detection part is for detecting an image region including a high spatial frequency component as a high-frequency region from the decoded image signal. A smoothing processing part is for performing smoothing processing to the decoded image signal corresponding to a predetermined region. A processing region setting part is for setting an image region in which the smoothing processing part is to perform smoothing processing to the decoded image signal are included. The processing region setting part sets at least a region in frames in which a correlation between frames is low and which is a flat region and not a high frequency region in the decoded image signals, as a processing region.
    Type: Application
    Filed: October 14, 2005
    Publication date: October 16, 2008
    Inventor: Kazuki Sawa
  • Publication number: 20060192896
    Abstract: Disclosed here is a frame-cyclic noise reduction employed for an image display device in which one field is divided into a plurality of sub-fields, and turned-on sub-fields are properly combined to provide image with gradation. The device detects an area where an edge portion of image becomes unclear, i.e., where sub-field fuzziness becomes worse, and controls a cyclic amount for the area in which sub-field fuzziness becomes worse so as to be different from that for other area, thereby decreasing noise.
    Type: Application
    Filed: January 28, 2005
    Publication date: August 31, 2006
    Inventor: Kazuki Sawa
  • Patent number: 6496194
    Abstract: A halftone display method utilizes an activation sequence, having a plurality of luminance blocks predefined in each frame or field to display an image and having redundancy, that enables one gray-scale level to be expressed by any one of a plurality of combinations of subframes (luminance blocks). When determining luminance blocks for use to display gray scale of an arbitrary first pixel, the luminance blocks to be used for the first pixel are selected in accordance with a predetermined rule, based on how the luminance blocks are used for a second pixel located in close proximity to the first pixel. In this way, by actively utilizing the redundancy of the activation sequence, the occurrence of moving-image false contours (false color contours) in video can be minimized, and also a motion compensation equalizing pulse method can be effectively applied to further improve the image display quality.
    Type: Grant
    Filed: October 27, 1999
    Date of Patent: December 17, 2002
    Assignees: Fujitsu Limited
    Inventors: Shigeo Mikoshiba, Tomokazu Shiga, Yiwen Zhu, Kiyoshi Igarashi, Kosaku Toda, Toshio Ueda, Kyoji Kariya, Takayuki Ooe, Kazuki Sawa