Patents by Inventor Kazuki Shigeta

Kazuki Shigeta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11193974
    Abstract: A failure diagnostic apparatus includes a path calculation unit which calculates, for each input pattern to a diagnosis target cell, a path affecting an output value of the diagnosis target cell when a failure is assumed as an activation path, a path classification unit which classifies the activation path associated with the input pattern for which the diagnosis target cell has passed a test and the activation path associated with the input pattern for which the diagnosis target cell has failed the test, a path narrowing unit which calculates a first failure candidate path, a second failure candidate path and a normal path of the diagnosis target cell based on classified activation paths, and a result output unit which outputs information on the first failure candidate path, the second failure candidate path and the normal path.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: December 7, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yukihisa Funatsu, Kazuki Shigeta
  • Publication number: 20210255242
    Abstract: A failure diagnostic apparatus includes a path calculation unit which calculates, for each input pattern to a diagnosis target cell, a path affecting an output value of the diagnosis target cell when a failure is assumed as an activation path, a path classification unit which classifies the activation path associated with the input pattern for which the diagnosis target cell has passed a test and the activation path associated with the input pattern for which the diagnosis target cell has failed the test, a path narrowing unit which calculates a first failure candidate path, a second failure candidate path and a normal path of the diagnosis target cell based on classified activation paths, and a result output unit which outputs information on the first failure candidate path, the second failure candidate path and the normal path.
    Type: Application
    Filed: December 14, 2020
    Publication date: August 19, 2021
    Inventors: Yukihisa FUNATSU, Kazuki SHIGETA
  • Publication number: 20210173100
    Abstract: Provided are a scintillator panel and an X-ray detector which have high sensitivity and sharpness. The scintillator panel includes a substrate and a scintillator layer containing a binder resin and a phosphor, wherein the scintillator panel further contains an organic compound having the maximum peak wavelength of light emission in the wavelength region of from 450 to 600 nm.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 10, 2021
    Applicant: Toray Industries, Inc.
    Inventors: Sho Miyao, Kazuki Shigeta, Hirotoshi Sakaino
  • Patent number: 9857482
    Abstract: The present invention provides a scintillator panel which is capable of utilizing light emitted by a phosphor at a high efficiency due to particles having a high refractive index being dispersed within a scintillator layer in a favorable state, which thus allows for a marked reduction in the amount of radiation exposure to a subject or the like, and which has a high luminance. The present invention also provides a scintillator panel including a substrate, and a scintillator layer containing metal compound particles and a phosphor, wherein the phosphor is covered by the metal compound at a coverage ratio of 5% or more.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: January 2, 2018
    Assignee: Toray Industries, Inc.
    Inventors: Kazuki Shigeta, Tsubasa Hamano
  • Publication number: 20170146671
    Abstract: The present invention provides a scintillator panel which is capable of utilizing light emitted by a phosphor at a high efficiency due to particles having a high refractive index being dispersed within a scintillator layer in a favorable state, which thus allows for a marked reduction in the amount of radiation exposure to a subject or the like, and which has a high luminance. The present invention also provides a scintillator panel including a substrate, and a scintillator layer containing metal compound particles and a phosphor, wherein the phosphor is covered by the metal compound at a coverage ratio of 5% or more.
    Type: Application
    Filed: June 29, 2015
    Publication date: May 25, 2017
    Applicant: TORAY INDUSTRIES, INC.
    Inventors: Kazuki Shigeta, Tsubasa Hamano
  • Patent number: 9159519
    Abstract: Disclosed are: a paste for an electron emission source, which enables omission of an activation process and is capable of emitting electrons at a low voltage, while exhibiting excellent adhesion to a cathode substrate; and an electron emission source which uses the paste for an electron emission source. Specifically disclosed is an electron emission source which is produced by subjecting a paste for an electron emission source containing the components (A)-(C) described below to a heat treatment. The electron emission source has cracks and carbon nanotubes project from the surfaces of the cracks. (A) carbon nanotubes (B) glass powder (C) at least one substance selected from the group consisting of metal salts, metal hydroxides, organic metal compounds, metal complexes, silane coupling agents and titanium coupling agents.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: October 13, 2015
    Assignee: TORAY INDUSTRIES, INC.
    Inventors: Takejiro Inoue, Kazuki Shigeta, Kazuki Goto, Sunkyu Park
  • Patent number: 8747545
    Abstract: The present invention provides a producing method of powder particles having an average particle diameter on the order of submicrons. Specifically, the producing method is a producing method of powder particles obtained by grinding a product to be ground by using plural grinding media, wherein the grinding media including at least one kind (grinding medium A) having an average particle diameter of 0.01 to 5 times and at least one kind (grinding medium B) having an average particle diameter of 10 to 450 times, with respect to the average particle diameter of the product to be ground before being ground, are used.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: June 10, 2014
    Assignee: TORAY Industries, Inc.
    Inventors: Kazuki Shigeta, Atsushi Ikeda
  • Patent number: 8241418
    Abstract: The present invention provides a producing method of powder particles having an average particle diameter on the order of submicrons. Specifically, the producing method is a producing method of powder particles obtained by grinding a product to be ground by using plural grinding media, wherein the grinding media including at least one kind (grinding medium A) having an average particle diameter of 0.01 to 5 times and at least one kind (grinding medium B) having an average particle diameter of 10 to 450 times, with respect to the average particle diameter of the product to be ground before being ground, are used.
    Type: Grant
    Filed: February 26, 2007
    Date of Patent: August 14, 2012
    Assignee: TORAY Industries, Inc.
    Inventors: Kazuki Shigeta, Atsushi Ikeda
  • Publication number: 20120177887
    Abstract: Disclosed are: a paste for an electron emission source, which enables omission of an activation process and is capable of emitting electrons at a low voltage, while exhibiting excellent adhesion to a cathode substrate; and an electron emission source which uses the paste for an electron emission source. Specifically disclosed is an electron emission source which is produced by subjecting a paste for an electron emission source containing the components (A)-(C) described below to a heat treatment. The electron emission source has cracks and carbon nanotubes project from the surfaces of the cracks. (A) carbon nanotubes (B) glass powder (C) at least one substance selected from the group consisting of metal salts, metal hydroxides, organic metal compounds, metal complexes, silane coupling agents and titanium coupling agents.
    Type: Application
    Filed: August 3, 2010
    Publication date: July 12, 2012
    Applicant: TORAY INDUSTRIES, INC.
    Inventors: Takejiro Inoue, Kazuki Shigeta, Kazuki Goto, Sunkyu Park
  • Patent number: 8206615
    Abstract: An object of the present invention is to provide a paste for an electron emission source, which can retain good electric contact between CNT and a cathode electrode, by containing an electrically conductive particle having a particle diameter within the optimal range. A paste for an electron emission source containing a carbon nanotube having a diameter of 1 nm or more and less than 10 nm, and an electrically conductive part having an average particle diameter of 0.1 to 1 ?m.
    Type: Grant
    Filed: February 20, 2008
    Date of Patent: June 26, 2012
    Assignee: Toray Industries, Inc.
    Inventors: Kazuki Shigeta, Takejiro Inoue, Atsushi Ikeda, Kazuki Goto
  • Publication number: 20110068202
    Abstract: The present invention provides a producing method of powder particles having an average particle diameter on the order of submicrons. Specifically, the producing method is a producing method of powder particles obtained by grinding a product to be ground by using plural grinding media, wherein the grinding media including at least one kind (grinding medium A) having an average particle diameter of 0.01 to 5 times and at least one kind (grinding medium B) having an average particle diameter of 10 to 450 times, with respect to the average particle diameter of the product to be ground before being ground, are used.
    Type: Application
    Filed: September 15, 2010
    Publication date: March 24, 2011
    Inventors: Kazuki Shigeta, Atsushi Ikeda
  • Publication number: 20100096972
    Abstract: An object of the present invention is to provide a paste for an electron emission source, which can retain good electric contact between CNT and a cathode electrode, by containing an electrically conductive particle having a particle diameter within the optimal range. A paste for an electron emission source containing a carbon nanotube having a diameter of 1 nm or more and less than 10 nm, and an electrically conductive part having an average particle diameter of 0.1 to 1 ?m.
    Type: Application
    Filed: February 20, 2008
    Publication date: April 22, 2010
    Inventors: Kazuki Shigeta, Takejiro Inoue, Atsushi Ikeda, Kazuki Goto
  • Publication number: 20090101737
    Abstract: The present invention provides a producing method of powder particles having an average particle diameter on the order of submicrons. Specifically, the producing method is a producing method of powder particles obtained by grinding a product to be ground by using plural grinding media, wherein the grinding media including at least one kind (grinding medium A) having an average particle diameter of 0.01 to 5 times and at least one kind (grinding medium B) having an average particle diameter of 10 to 450 times, with respect to the average particle diameter of the product to be ground before being ground, are used.
    Type: Application
    Filed: February 26, 2007
    Publication date: April 23, 2009
    Inventors: Kazuki Shigeta, Atsushi Ikeda
  • Patent number: 7120829
    Abstract: The present invention provides a technique relating to a failure propagation path estimate system which can realize an estimate process by adding the measurement result to the failure location estimate results estimated prior to the measurement, and which can realize high-speed re-calculation of only part of a large-scale circuit relating to the measurement point. As shown in FIG. 1, the failure propagation path estimate system according to the present embodiment is generally provided with an input device 1 such as a keyboard or an interface for external devices, a failure propagation path estimate processor (failure propagation path estimate device, error propagation path estimate processor) 2 operated under the control of a program, a storage device 4 for storing information necessary for the failure propagation path estimate process, and an output device 5 such as a display device, a printer or an interface for external devices.
    Type: Grant
    Filed: July 12, 2002
    Date of Patent: October 10, 2006
    Assignee: NEC Electronics Corporation
    Inventor: Kazuki Shigeta
  • Patent number: 6915494
    Abstract: A fault analyzing system presumes fault propagation paths for specifying nodes related to fault terminals once on plural time planes, and merges pieces of related fault terminal information representative of the fault terminals related to the nodes on different time planes in different manners so that plural list of plural kinds of fault are drawn up without repeating the time-consuming presumption.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: July 5, 2005
    Assignee: NEC Electronics Corporation
    Inventor: Kazuki Shigeta
  • Patent number: 6857094
    Abstract: Disclosed is a system for inferring faulty locations in a combinational logic circuit by tracing a fault propagation path from a faulty terminal through repetition of logic decisions and implications. The system infers a logic state by repeating logic state decisions and implications and comparing the logic state with an expected value, which corresponds to a normally operating logic state, thereby inferring a fault propagation path in the logic circuit.
    Type: Grant
    Filed: February 12, 2002
    Date of Patent: February 15, 2005
    Assignee: NEC Electronics Corporation
    Inventor: Kazuki Shigeta
  • Patent number: 6697981
    Abstract: In evaluating the location of a failure in a logic circuit including gates defined in a hierarchical manner, the present invention discloses a system capable of evaluating the location of a failure by referring to the circuitry of a gate described by a basic gate without creating any special databases that are dedicated to evaluating the location of a failure. In this system, expected value setting device obtains an expected value of a target gate inside the logic circuit by an IF-THEN operation in an output direction, logical state evaluating device obtains a logical state of the target gate inside the logic circuit by an IF-THEN operation in an input/output direction, and a failure propagation path inside the target gate is obtained by comparing the expected value with the logical state.
    Type: Grant
    Filed: January 29, 2001
    Date of Patent: February 24, 2004
    Assignee: NEC Corporation
    Inventor: Kazuki Shigeta
  • Patent number: 6560738
    Abstract: A gate connected to an input side of a normal signal line estimated-as in a logical state equal to an expected value with an implication operation is detected as a newly implication-capable gate, and a signal line on an output side of a gate estimated as in a logical state equal to the expected value with an implication operation for the implication-capable gate is initialized to a logical state before the implication operation. A signal line in which a logical contradiction occurs in the logical state estimated with the implication operation is registered, and the number of occurrences thereof is recorded. Additionally, the result of the implication operation is stored as history information, and when the number of occurrences of logical contradictions exceeds an allowable number, the history information is traced to initialize a logical state of a signal line causing the logical contradiction to a state before the implication operation until the number falls within the allowable number.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: May 6, 2003
    Assignee: NEC Electronics Corporation
    Inventor: Kazuki Shigeta
  • Publication number: 20030066000
    Abstract: The present invention provides a technique relating to a failure propagation path estimate system which can realize an estimate process by adding the measurement result to the failure location estimate results estimated prior to the measurement, and which can realize high-speed re-calculation of only part of a large-scale circuit relating to the measurement point.
    Type: Application
    Filed: July 12, 2002
    Publication date: April 3, 2003
    Applicant: NEC Corporation
    Inventor: Kazuki Shigeta
  • Publication number: 20020112207
    Abstract: Disclosed is a system for inferring faulty locations in a combinational logic circuit by tracing a fault propagation path from a faulty terminal through repetition of logic decisions and implications. The system infers a logic state in a combinational logic circuit by repeating logic state decisions and implications and comparing the logic state with an expected value, which corresponds to a logic state that prevails when the combinational logic circuit operates normally, thereby inferring a fault propagation path in the combinational logic circuit.
    Type: Application
    Filed: February 12, 2002
    Publication date: August 15, 2002
    Applicant: NEC CORPORATION
    Inventor: Kazuki Shigeta