Patents by Inventor Kazuki Tanemura
Kazuki Tanemura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220131146Abstract: The present invention relates to a secondary battery and an electronic device. The secondary battery includes a positive electrode active material which exhibits a broad peak at around 4.55 V in a dQ/dVvsV curve obtained when the charge depth is increased. The secondary battery includes a positive electrode active material which, even when the charge voltage is greater than or equal to 4.6 V and less than or equal to 4.8 V and the charge depth is greater than or equal to 0.8 and less than 0.9, does not have the H1-3 type structure and can maintain a crystal structure where a shift in CoO2 layers is inhibited. The broad peak at around 4.55 V in the dQ/dVvsV curve indicates that a change in the energy necessary for extraction of lithium at around the voltage is small and a change in the crystal structure is small. Accordingly, the positive electrode active material hardly suffers a shift in CoO2 layers and a volume change and is relatively stable even when the charge depth is large.Type: ApplicationFiled: October 21, 2021Publication date: April 28, 2022Inventors: Jo SAITO, Yohei MOMMA, Kunihiro FUKUSHIMA, Shunsuke HOSOUMI, Kazuki TANEMURA, Tetsuya KAKEHATA, Shunpei YAMAZAKI, Toshikazu OHNO, Mayumi MIKAMI, Tatsuyoshi TAKAHASHI, Kazuya SHIMADA
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Publication number: 20220073367Abstract: The present invention relates to a method for manufacturing a secondary battery and a secondary battery. A method for manufacturing a positive electrode active material with high charge and discharge capacity is provided. A method for manufacturing a positive electrode active material with high charging and discharging voltages is provided. A method for manufacturing a positive electrode active material with little deterioration is provided. The positive electrode active material is manufactured through a step of forming a composite oxide that contains lithium, nickel, manganese, cobalt, and oxygen; and a step of mixing the composite oxide and a calcium compound, and then heating the mixture at a temperature higher than or equal to 500° C. and lower than or equal to 1100° C. for 2 hours to 20 hours. By the heating, calcium is distributed at a preferred concentration in a surface portion of the positive electrode active material.Type: ApplicationFiled: September 1, 2021Publication date: March 10, 2022Inventors: Yohei MOMMA, Mayumi MIKAMI, Yusuke YOSHITANI, Kazuki TANEMURA
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Patent number: 11257722Abstract: A semiconductor device with a high threshold voltage is provided. A first conductor positioned over a substrate, a first insulator positioned over the first conductor, a first oxide positioned in contact with the top surface of the first insulator, a second insulator positioned in contact with the top surface of the first oxide, a second oxide positioned over the second insulator, a third insulator positioned over the second oxide, and a second conductor positioned over the third insulator are included. A mixed layer is formed between the first insulator and the first oxide. The mixed layer contains at least one of atoms contained in the first insulator and at least one of atoms contained in the first oxide. The mixed layer has fixed negative charge.Type: GrantFiled: July 18, 2018Date of Patent: February 22, 2022Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kazuki Tanemura, Etsuko Kamata, Hiromi Sawai, Daisuke Matsubayashi
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Patent number: 11217668Abstract: A miniaturized transistor with reduced parasitic capacitance and highly stable electrical characteristics is provided. High performance and high reliability of a semiconductor device including the transistor is achieved. A first conductor is formed over a substrate, a first insulator is formed over the first conductor, a layer that retains fixed charges is formed over the first insulator, a second insulator is formed over the layer that retains fixed charges, and a transistor is formed over the second insulator. Threshold voltage Vth is controlled by appropriate adjustment of the thicknesses of the first insulator, the second insulator, and the layer that retains fixed charges.Type: GrantFiled: January 8, 2020Date of Patent: January 4, 2022Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tetsuhiro Tanaka, Kazuki Tanemura, Daisuke Matsubayashi
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Publication number: 20210125823Abstract: A method for depositing a metal oxynitride film by epitaxial growth at a low temperature is provided. It is a method for manufacturing a metal oxynitride film, in which the metal oxynitride film is epitaxially grown on a single crystal substrate by a sputtering method using an oxide target with a gas containing a nitrogen gas introduced. The oxide target contains zinc, the substrate during the deposition of the metal oxynitride film is higher than or equal to 80° C. and lower than or equal to 400° C., and the flow rate of the nitrogen gas is greater than or equal to 50% and lower than or equal to 100% of the total flow rate of the gas.Type: ApplicationFiled: June 24, 2019Publication date: April 29, 2021Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Kazuki TANEMURA, Shota SAMBONSUGE, Naoki OKUNO
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Publication number: 20210090961Abstract: A semiconductor device with a high threshold voltage is provided. A first conductor positioned over a substrate, a first insulator positioned over the first conductor, a first oxide positioned in contact with the top surface of the first insulator, a second insulator positioned in contact with the top surface of the first oxide, a second oxide positioned over the second insulator, a third insulator positioned over the second oxide, and a second conductor positioned over the third insulator are included. A mixed layer is formed between the first insulator and the first oxide. The mixed layer contains at least one of atoms contained in the first insulator and at least one of atoms contained in the first oxide. The mixed layer has fixed negative charge.Type: ApplicationFiled: July 18, 2018Publication date: March 25, 2021Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Kazuki TANEMURA, Etsuko KAMATA, Hiromi SAWAI, Daisuke MATSUBAYASHI
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Publication number: 20200152671Abstract: A miniaturized transistor with reduced parasitic capacitance and highly stable electrical characteristics is provided. High performance and high reliability of a semiconductor device including the transistor is achieved. A first conductor is formed over a substrate, a first insulator is formed over the first conductor, a layer that retains fixed charges is formed over the first insulator, a second insulator is formed over the layer that retains fixed charges, and a transistor is formed over the second insulator. Threshold voltage Vth is controlled by appropriate adjustment of the thicknesses of the first insulator, the second insulator, and the layer that retains fixed charges.Type: ApplicationFiled: January 8, 2020Publication date: May 14, 2020Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Tetsuhiro TANAKA, Kazuki TANEMURA, Daisuke MATSUBAYASHI
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Patent number: 10553690Abstract: A miniaturized transistor with reduced parasitic capacitance and highly stable electrical characteristics is provided. High performance and high reliability of a semiconductor device including the transistor is achieved. A first conductor is formed over a substrate, a first insulator is formed over the first conductor, a layer that retains fixed charges is formed over the first insulator, a second insulator is formed over the layer that retains fixed charges, and a transistor is formed over the second insulator. Threshold voltage Vth is controlled by appropriate adjustment of the thicknesses of the first insulator, the second insulator, and the layer that retains fixed charges.Type: GrantFiled: July 27, 2016Date of Patent: February 4, 2020Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tetsuhiro Tanaka, Kazuki Tanemura, Daisuke Matsubayashi
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Patent number: 9991393Abstract: A semiconductor device includes a first conductor, a second conductor, a first semiconductor, a second semiconductor, a third semiconductor, and an insulator. The second semiconductor is in contact with an upper surface of the first semiconductor. The first conductor overlaps with the second semiconductor. The insulator is located between the first conductor and the first semiconductor. The second conductor is in contact with an upper surface of the second semiconductor. The third semiconductor is in contact with the upper surface of the first semiconductor, the upper surface of the second semiconductor, and an upper surface of the second conductor.Type: GrantFiled: October 8, 2015Date of Patent: June 5, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tetsuhiro Tanaka, Kazuki Tanemura
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Patent number: 9929407Abstract: A non-aqueous secondary battery which has high charge-discharge capacity, can be charged and discharged at high speed, and has little deterioration in battery characteristics due to charge and discharge is provided. A negative electrode includes a current collector and an active material layer. The current collector includes a plurality of protrusion portions extending in a substantially perpendicular direction and a base portion connected to the plurality of protrusion portions. The protrusion portions and the base portion are formed using the same material containing titanium. Top surfaces and side surfaces of the protrusion portions and a top surface of the base portion are covered with the active material layer. The active material layer includes a plurality of whiskers. The active material layer may be covered with graphene.Type: GrantFiled: December 20, 2012Date of Patent: March 27, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kazuki Tanemura, Toshihiko Takeuchi, Taiga Muraoka
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Patent number: 9812466Abstract: A highly reliable semiconductor device that is suitable for high-speed operation is provided. A semiconductor device includes a first circuit, a second circuit, and a third circuit. The first circuit has an arithmetic processing function. The second circuit includes a memory circuit. The memory circuit includes a transistor which includes a first conductor, a second conductor, a first insulator, a second insulator, and a semiconductor. The first conductor includes a region overlapping the semiconductor with the first insulator positioned between the first conductor and the semiconductor. The second conductor includes a region overlapping the semiconductor with the second insulator positioned between the second conductor and the semiconductor. The first conductor is capable of selecting on or off of the transistor. The third circuit is electrically connected to the second conductor, and is capable of changing the potential of the second conductor in synchronization with an operation of the transistor.Type: GrantFiled: August 4, 2015Date of Patent: November 7, 2017Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tomoaki Atsumi, Masayuki Sakakura, Yoshitaka Yamamoto, Jun Koyama, Tetsuhiro Tanaka, Kazuki Tanemura
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Patent number: 9755083Abstract: Electrical characteristics of a semiconductor device including the oxide semiconductor are improved. Furthermore, a highly reliable transistor with small variation in electrical characteristics is manufactured. An oxynitride insulating film functioning as a base insulating film and a transistor in contact with the oxynitride insulating film are provided. The transistor includes an oxide semiconductor film in contact with the oxynitride insulating film functioning as a base insulating film. The total amount of gas having a mass-to-charge ratio of 30 released from the oxynitride insulating film by heat treatment and double of the amount of a gas having a mass-to-charge ratio of 32 released from the oxynitride insulating film by heat treatment is greater than or equal to 5×1015/cm2 and less than or equal to 5×1016/cm2, or greater than or equal to 5×1015/cm2 and less than or equal to 3×1016/cm2.Type: GrantFiled: August 24, 2016Date of Patent: September 5, 2017Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kosei Noda, Satoshi Toriumi, Kazuki Tanemura
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Patent number: 9590115Abstract: A semiconductor device includes a first conductor, a second conductor, a first insulator, a second insulator, a third insulator, a semiconductor, and an electron trap layer. The semiconductor includes a channel formation region. The electron trap layer overlaps with the channel formation region with the second insulator interposed therebetween. The first conductor overlaps with the channel formation region with the first insulator interposed therebetween. The second conductor overlaps with the electron trap layer with the third insulator interposed therebetween. The second conductor does not overlap with the channel formation region.Type: GrantFiled: November 16, 2015Date of Patent: March 7, 2017Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tetsuhiro Tanaka, Daisuke Matsubayashi, Kazuki Tanemura
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Publication number: 20170040424Abstract: A miniaturized transistor with reduced parasitic capacitance and highly stable electrical characteristics is provided. High performance and high reliability of a semiconductor device including the transistor is achieved. A first conductor is formed over a substrate, a first insulator is formed over the first conductor, a layer that retains fixed charges is formed over the first insulator, a second insulator is formed over the layer that retains fixed charges, and a transistor is formed over the second insulator. Threshold voltage Vth is controlled by appropriate adjustment of the thicknesses of the first insulator, the second insulator, and the layer that retains fixed charges.Type: ApplicationFiled: July 27, 2016Publication date: February 9, 2017Inventors: Tetsuhiro TANAKA, Kazuki TANEMURA, Daisuke MATSUBAYASHI
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Patent number: 9537014Abstract: Threshold voltage adjustment method of a semiconductor device is provided. In a semiconductor device in which at least one of transistors included in an inverter includes a semiconductor, a source electrode or a drain electrode electrically connected to the semiconductor, a gate electrode, and a charge trap layer provided between the gate electrode and the semiconductor, the potential of the gate electrode of the transistor that is higher than those of the source electrode and the drain electrode is held for a short time of 5 s or shorter, whereby electrons are trapped in the charge trap layer and the threshold voltage is increased. At this time, when the potential differences between the gate electrode and the source electrode, and the gate electrode and the drain electrode are different from each other, the threshold voltage of the transistor of the semiconductor device becomes appropriate.Type: GrantFiled: May 28, 2015Date of Patent: January 3, 2017Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kazuki Tanemura, Tetsuhiro Tanaka, Kosei Noda
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Publication number: 20160365454Abstract: Electrical characteristics of a semiconductor device including the oxide semiconductor are improved. Furthermore, a highly reliable transistor with small variation in electrical characteristics is manufactured. An oxynitride insulating film functioning as a base insulating film and a transistor in contact with the oxynitride insulating film are provided. The transistor includes an oxide semiconductor film in contact with the oxynitride insulating film functioning as a base insulating film. The total amount of gas having a mass-to-charge ratio of 30 released from the oxynitride insulating film by heat treatment and double of the amount of a gas having a mass-to-charge ratio of 32 released from the oxynitride insulating film by heat treatment is greater than or equal to 5×1015/cm2 and less than or equal to 5×1016/cm2, or greater than or equal to 5×1015/cm2 and less than or equal to 3×1016/cm2.Type: ApplicationFiled: August 24, 2016Publication date: December 15, 2016Inventors: Kosei NODA, Satoshi TORIUMI, Kazuki TANEMURA
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Patent number: 9450102Abstract: Electrical characteristics of a semiconductor device including the oxide semiconductor are improved. Furthermore, a highly reliable transistor with small variation in electrical characteristics is manufactured. An oxynitride insulating film functioning as a base insulating film and a transistor in contact with the oxynitride insulating film are provided. The transistor includes an oxide semiconductor film in contact with the oxynitride insulating film functioning as a base insulating film. The total amount of gas having a mass-to-charge ratio of 30 released from the oxynitride insulating film by heat treatment and double of the amount of a gas having a mass-to-charge ratio of 32 released from the oxynitride insulating film by heat treatment is greater than or equal to 5×1015/cm2 and less than or equal to 5×1016/cm2, or greater than or equal to 5×1015/cm2 and less than or equal to 3×1016/cm2.Type: GrantFiled: April 14, 2014Date of Patent: September 20, 2016Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kosei Noda, Satoshi Toriumi, Kazuki Tanemura
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Publication number: 20160190338Abstract: To provide a semiconductor device suitable for high reliability and high-speed operation. The semiconductor device includes a first conductor, a first insulator, a second insulator, a semiconductor, and an electron trap layer. The semiconductor includes a channel formation region. The first conductor includes a region overlapping with the channel formation region with the first insulator provided therebetween. The second insulator is placed to include a region in contact with a side surface of the first conductor. The electron trap layer is placed to face the first conductor with the second insulator provided therebetween.Type: ApplicationFiled: December 21, 2015Publication date: June 30, 2016Inventors: Tetsuhiro TANAKA, Daisuke MATSUBAYASHI, Kazuki TANEMURA
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Publication number: 20160149045Abstract: A semiconductor device includes a first conductor, a second conductor, a first insulator, a second insulator, a third insulator, a semiconductor, and an electron trap layer. The semiconductor includes a channel formation region. The electron trap layer overlaps with the channel formation region with the second insulator interposed therebetween. The first conductor overlaps with the channel formation region with the first insulator interposed therebetween. The second conductor overlaps with the electron trap layer with the third insulator interposed therebetween. The second conductor does not overlap with the channel formation region.Type: ApplicationFiled: November 16, 2015Publication date: May 26, 2016Inventors: Tetsuhiro TANAKA, Daisuke MATSUBAYASHI, Kazuki TANEMURA
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Patent number: 9337475Abstract: A power storage device in which silicon is used as a negative electrode active material layer and which can have an improved performance such as higher discharge capacity, and a method for manufacturing the power storage device are provided. A power storage device includes a current collector and a silicon layer having a function as an active material layer over the current collector. The silicon layer includes a thin film portion in contact with the current collector, a plurality of bases, and a plurality of whisker-like protrusions extending from the plurality of bases. A protrusion extending from one of the plurality of bases is partly combined with a protrusion extending from another one of the plurality of bases.Type: GrantFiled: August 15, 2012Date of Patent: May 10, 2016Assignee: Semiconductor Energy Laboratory Co., LTD.Inventors: Toshihiko Takeuchi, Minoru Takahashi, Takeshi Osada, Teppei Oguni, Kazuki Tanemura