Abstract: An electronic device having an eye tracking function is provided. The electronic device includes a display device and an optical system. The display device includes a first light-emitting element, a second light-emitting element, a sensor portion, and a driver circuit portion. The sensor portion includes a light-receiving element. The first light-emitting element has a function of emitting infrared light or visible light. The second light-emitting element has a function of emitting light of a color different from that of light emitted from the first light-emitting element. When the first light-emitting element emits infrared light, the light-receiving element has a function of detecting the infrared light that is emitted from the first light-emitting element and reflected by an eyeball of a user.

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a cell array performing a product-sum operation of a first layer and a product-sum operation of a second layer in an artificial neural network, a first circuit from which first data is input to the cell array, and a second circuit to which second data is output from the cell array. The cell array includes a plurality of cells. The cell array includes a first region and a second region. In a first period, the first region is supplied with the t-th (t is a natural number greater than or equal to 2) first data from the first circuit and outputs the t-th second data according to the product-sum operation of the first layer to the second circuit. In the first period, the second region is supplied with the (t+1)-th first data from the first circuit and outputs the (t+1)-th second data according to the product-sum operation of the second layer to the first circuit.

Abstract: A lens portion of a display device includes: a first lens arranged between a light guide plate and a light-emitting element portion, and having a plurality of first prisms arranged on a first light-exiting surface; and a second lens arranged between the first lens and the light-emitting element portion, and having a plurality of second prisms arranged on a second light-exiting surface arranged at a position facing a light-entering surface. The first lens includes a plurality of diffusing prisms arranged on the light-entering surface and capable of diffusing light emitted from the second lens and introducing said light into the first lens.

Abstract: A performance of an apparatus is improved. A display apparatus includes: a light guide panel; a light source unit including a plurality of light emitting diode elements arranged in an X direction at a position facing a side surface of the light guide panel; and a plurality of lenses arranged in the X direction between the light guide panel and the light source unit and adhered to each other while sandwiching an adhesive layer allowing visible light to penetrate therethrough. Each of the plurality of lenses includes a surface facing the light source unit, a surface opposite to this surface, and a side surface (lens side surface) crossing these surfaces and being adhered to the adhesive layer. The adhesive layer is arranged between the sides surfaces facing each other.

Abstract: A display device includes a display panel including a polymer-dispersed liquid crystal layer between a pair of substrates, a transparent substrate disposed on at least one side of the display panel, and a lighting unit configured to project light from the side of the transparent substrate. The lighting unit includes at least one light source, at least one light guide incident with the light emitted from the light source, and a support member having an L-shaped cross section and extending along one side of the display panel to which the at least one light source and the at least one light guide are fixed. The at least one light source and the at least one light guide are disposed on different sides of the support member. The lighting unit is fixed to the transparent substrate or the display panel by the support member.

Abstract: To provide a novel electronic device. The electronic device includes a housing and a display device. The display device includes a first layer, a second layer, and a third layer. The first layer, the second layer, and the third layer are provided in different layers. The first layer includes a driver circuit and an arithmetic circuit. The second layer includes pixel circuits and a cell array. The third layer includes light-receiving devices and light-emitting devices. The pixel circuits each have a function of controlling light emission of the light-emitting device. The driver circuit has a function of controlling the pixel circuits. The arithmetic circuit has a function of performing arithmetic processing on the basis of first data corresponding to currents output from the light-receiving devices and second data corresponding to a potential held in the cell array.

Abstract: A lens portion of a display device includes: a first lens arranged between a light guide plate and a light-emitting element portion, and having a plurality of first prisms arranged on a first light-exiting surface; and a second lens arranged between the first lens and the light-emitting element portion, and having a plurality of second prisms arranged on a second light-exiting surface arranged at a position facing a light-entering surface. The first lens includes a plurality of diffusing prisms arranged on the light-entering surface and capable of diffusing light emitted from the second lens and introducing said light into the first lens.

Abstract: A semiconductor device with low power consumption is provided. The semiconductor device includes a first transistor, a second transistor, and a capacitor. The first transistor includes a first gate and a first back gate, and the second transistor includes a second gate and a second back gate. A gate insulating layer for the first back gate has ferroelectricity. The first transistor has a function of, when being in an off state, retaining a first potential corresponding to first data. The second transistor has a function of making an output current flow between a source and a drain of the second transistor.

Abstract: A novel semiconductor device is provided. An analog signal is converted into a digital signal using a comparison portion comparing two current values, a control portion, and a current output digital-analog conversion portion. The control portion has a function of generating a sign bit showing a magnitude relation between the two current values, a function of converting a difference between the two current values into a digital signal by successive approximation, and a function of outputting the sign bit and the digital signal.

Abstract: A highly reliable memory device is provided. The memory device includes a first conductor, a second conductor above the first conductor, a third conductor above the second conductor, a fourth conductor above the third conductor, a fifth conductor above the fourth conductor, a sixth conductor above the fifth conductor, a seventh conductor, a first insulator, a second insulator, a first semiconductor, and a second semiconductor. At least third conductor and the fourth conductor have an opening. The first insulator, the first semiconductor, the second insulator, and the second semiconductor are provided in this order on an inner surface of the opening. The seventh conductor is provided between the first semiconductor and the second insulator in a region between the third conductor and the second insulator. The first semiconductor is electrically connected to the second conductor and the fifth conductor. The second semiconductor is electrically connected to the first conductor and the sixth conductor.

Abstract: Provided is a semiconductor device having a novel structure. A first transistor, a second transistor, a third transistor, and a capacitor are included. The first transistor has a function of retaining a first potential corresponding to first data supplied to a gate of the third transistor through the first transistor when being in an off state. The capacitor has a function of changing the first potential retained in the gate of the third transistor into a second potential in accordance with a change in potential corresponding to second data supplied to one electrode of the capacitor. The second transistor has a function of setting a potential of one of a source and a drain of the third transistor to a potential corresponding to a potential of a gate of the second transistor. The third transistor has a function of supplying output current corresponding to a potential of the gate of the third transistor to the other of the source and the drain of the third transistor.

Abstract: A control circuit of a secondary battery with a novel structure is provided. The control circuit of a secondary battery includes a first transistor, a first voltage generation circuit generating a first voltage, and a second voltage generation circuit generating a second voltage. The first voltage generation circuit includes a second transistor and a first capacitor. The second voltage generation circuit includes a third transistor and a second capacitor. The difference between the first voltage and the second voltage is set in accordance with the threshold voltage of the first transistor. When the first transistor includes a back gate, a voltage retention circuit having a function of retaining the voltage of the back gate is included. The voltage retention circuit includes a fourth transistor and a third capacitor. The third capacitor includes a ferroelectric layer between a pair of electrodes.

Abstract: A novel semiconductor device is provided. A memory string extends in a Z direction. The memory string achieves high-speed operation by using an oxide semiconductor for a semiconductor layer. The memory string includes a MONOS memory cell. A tunnel layer is provided on a control gate side, and a block layer is provided on a semiconductor side. During erase operation, a hole is injected into a charge accumulation layer from the control gate side.

Abstract: A semiconductor device with a high driving speed is provided. The semiconductor device includes first to fourth cells, a converter circuit, and first to fourth wirings. The first and second cells make a first current and a second current each corresponding to the product of first data and second data flow in the first wiring and the second wiring, respectively. The third and fourth cells make base currents in the same amount flow in the first and second wirings. The converter circuit outputs, from an output terminal thereof, a voltage corresponding to the differential current between the sum of the first current and the base current flowing in the first wiring and the sum of the second current and the base current flowing in the second wiring.

Abstract: A novel semiconductor device is provided. A memory string, which extends in the Z direction and includes a conductor and an oxide semiconductor, intersects with a plurality of wirings CG extending in the Y direction. The conductor is placed along a center axis of the memory string, and the oxide semiconductor is concentrically placed outside the conductor. The conductor is electrically connected to the oxide semiconductor. An intersection portion of the memory string and the wiring CG functions as a transistor. In addition, the intersection portion functions as a memory cell.

Abstract: A novel semiconductor device is provided. A structure body extending in a first direction, a first conductor extending in a second direction, and a second conductor extending in the second direction are provided. In a first intersection portion where the structure body and the first conductor intersect with each other, a first insulator, a first semiconductor, a second insulator, a second semiconductor, a third insulator, a fourth insulator, and a fifth insulator are provided concentrically around a third conductor. In a second intersection portion where the structure body and the second conductor intersect with each other, the first insulator, the first semiconductor, the second insulator, a fourth conductor, the second semiconductor, and the third insulator are provided concentrically around the third conductor.

Abstract: A memory device with a small number of wirings using a NAND flash memory having a three-dimensional structure with a large number of stacked memory cell layers is provided. A decoder is formed using an OS transistor. An OS transistor can be formed by a method such as a thin film method, whereby the decoder can be provided to be stacked above the NAND flash memory having a three-dimensional structure. This can reduce the number of wirings provided substantially perpendicular to the memory cell layers.

Abstract: A semiconductor device that is suitable for high integration is provided. A first layer provided with a first transistor including an oxide semiconductor, over a substrate; a second layer over the first layer; a third layer provided with a second transistor including an oxide semiconductor, over the second layer; a fourth layer between the first layer and the second layer; and a fifth layer between the second layer and the third layer are included. The total internal stress of the first layer and the total internal stress of the third layer act in a first direction, the total internal stress of the second layer acts in the direction opposite to the first direction, and the fourth layer and the fifth layer each include a film having a barrier property.

Abstract: A memory device with large storage capacity is provided. A NAND memory device includes a plurality of connected memory cells each provided with a writing transistor, a reading transistor, and a capacitor. An oxide semiconductor is used in a semiconductor layer of the writing transistor. The reading transistor includes a back gate. When a reading voltage is applied to the back gate, information stored in the memory cell is read out.

Abstract: A semiconductor device is provided in which power consumption is reduced and an increase in circuit area is inhibited. The semiconductor device includes a high frequency amplifier circuit, an envelope detection circuit, and a power supply circuit. The power supply circuit has a function of supplying a power supply potential to the high frequency amplifier circuit, an output of the high frequency amplifier circuit is connected to the envelope detection circuit, and an output of the envelope detection circuit is connected to the power supply circuit. The power supply circuit can reduce the power consumption by changing the power supply potential in accordance with the output of the high frequency amplifier circuit. The use of an OS transistor in the envelope detection circuit can inhibit an increase in circuit area.