Patents by Inventor Kazuki Yokota
Kazuki Yokota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240101572Abstract: The present invention provides a compound having a PLD inhibitory activity. The present invention provides a compound of the following structural formula, and the like, or a pharmaceutically acceptable salt thereof. wherein each symbol is as defined in the description.Type: ApplicationFiled: June 15, 2023Publication date: March 28, 2024Inventors: Masahiro YOKOTA, Tetsudo KAYA, Makoto TORIZUKA, Yasuaki NAKAYAMA, Taku IKENOGAMI, Katsuya MAEDA, Kazuki OTAKE, Kentaro SAKURAI
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Patent number: 10224395Abstract: In an element isolation region defining an element formation region, there is formed an element isolation unit including an element isolation unit and the other element isolation unit. The other element isolation unit is arranged in a direction intersecting a direction in which the element isolation unit extends from the element isolation unit. The element isolation unit includes a sidewall oxide film formed in a trench, a titanium film, a titanium nitride film, and a tungsten film. The tungsten film is formed to cover the bottom surface of a trench in the element isolation unit and to close an opening end of a trench in the other element isolation unit. A plug is formed in contact with the tungsten film of the element isolation unit.Type: GrantFiled: July 13, 2017Date of Patent: March 5, 2019Assignee: Renesas Electronics CorporationInventor: Kazuki Yokota
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Patent number: 9887085Abstract: A photoresist is exposed to light under a condition that sensitivity of a second portion of the photoresist on a recessed portion of a base layer is higher than sensitivity of a first portion of the photoresist on a projecting portion of the base layer.Type: GrantFiled: August 2, 2016Date of Patent: February 6, 2018Assignee: Renesas Electronics CorporationInventor: Kazuki Yokota
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Publication number: 20180019303Abstract: In an element isolation region defining an element formation region, there is formed an element isolation unit including an element isolation unit and the other element isolation unit. The other element isolation unit is arranged in a direction intersecting a direction in which the element isolation unit extends from the element isolation unit. The element isolation unit includes a sidewall oxide film formed in a trench, a titanium film, a titanium nitride film, and a tungsten film. The tungsten film is formed to cover the bottom surface of a trench in the element isolation unit and to close an opening end of a trench in the other element isolation unit. A plug is formed in contact with the tungsten film of the element isolation unit.Type: ApplicationFiled: July 13, 2017Publication date: January 18, 2018Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Kazuki YOKOTA
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Publication number: 20170040163Abstract: A photoresist is exposed to light under a condition that sensitivity of a second portion of the photoresist on a recessed portion of a base layer is higher than sensitivity of a first portion of the photoresist on a projecting portion of the base layer.Type: ApplicationFiled: August 2, 2016Publication date: February 9, 2017Applicant: Renesas Electronics CorporationInventor: Kazuki YOKOTA
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Patent number: 6801313Abstract: The present invention relates to an overlay mark used for the measurement of the overlay accuracy between layered patterns and alignment at the time of exposure; which has a grooved pattern surrounding a mark pattern that is formed by engraving a groove or an indent in a prescribed position on a layer where a circuit pattern is formed so as to protect this mark pattern from being deformed by thermal expansion or contraction of this layer. The present invention enables to form a multi-layered circuit pattern with a high accuracy and a high yield in production, even in the formation of a minute and densely-spaced circuit pattern.Type: GrantFiled: July 27, 2000Date of Patent: October 5, 2004Assignee: NEC Electronics CorporationInventor: Kazuki Yokota
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Patent number: 6498401Abstract: An alignment mark set is provided, which facilitates the formation of a desired contour of each alignment mark and which suppresses the degradation of measurement accuracy for alignment of patterns. This alignment mark set comprises: (a) a first alignment mark formed in an exposure area; the area having a periphery, first central axis, and a second central axis perpendicular to the first axis; the first alignment mark being located near the first central axis and apart from the second axis; (b) a second alignment mark formed in the exposure area; the second alignment mark being located near the second central axis and apart from the first axis; and (c) when the exposure areas are regularly arranged in such a way as to have a same orientation in a plane, each of the first and second alignment marks in one of the sets is not located close to the first and second alignment marks in another of the sets, thereby ensuring irradiation of exposing light to all the areas.Type: GrantFiled: February 20, 2001Date of Patent: December 24, 2002Assignee: NEC CorporationInventor: Kazuki Yokota
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Patent number: 6477700Abstract: A reticle has a main pattern to be transferred to a photo-sensitive layer and surrounded by a non-transparent layer, and a discriminative pattern loops in the non-transparent layer so as to define an area to be inspected for serious defects, wherein the discriminative pattern is implemented by plural non-transparent portions such as strips arranged at intervals less than the minimum width to be transferred at the maximum resolution of the reduction projection aligner; however, the discriminative pattern or the plural non-transparent portions occupy a looped area wider than a minimum width to be recognized by a pattern recognition system so that the discriminative pattern clearly defines the area to be inspected regardless of the resolution.Type: GrantFiled: March 16, 2000Date of Patent: November 5, 2002Assignee: NEC CorporationInventor: Kazuki Yokota
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Publication number: 20010021548Abstract: An alignment mark set is provided, which facilitates the formation of a desired contour of each alignment mark and which suppresses the degradation of measurement accuracy for alignment of patterns. This alignment mark set comprises: (a) a first alignment mark formed in an exposure area; the area having a periphery, first central axis, and a second central axis perpendicular to the first axis; the first alignment mark being located near the first central axis and apart from the second axis; (b) a second alignment mark formed in the exposure area; the second alignment mark being located near the second central axis and apart from the first axis; and (c) when the exposure areas are regularly arranged in such a way as to have a same orientation in a plane, each of the first and second alignment marks in one of the sets is not located close to the first and second alignment marks in another of the sets, thereby ensuring irradiation of exposing light to all the areas.Type: ApplicationFiled: February 20, 2001Publication date: September 13, 2001Applicant: NEC CorporationInventor: Kazuki Yokota
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Patent number: 6104019Abstract: The first detection unit detects a focus search state in which focus search is required. The second detection unit detects one of the plurality of layers currently being accessed, i.e., information is being recorded or reproduced. Then, the focus search unit moves a light beam relative to the plurality of layers to obtain a focused state of the light beam on a desired one of the plurality of layers when the first detection unit detects the focus search state. Importantly, the focus search unit moves the light beam from one side of two surfaces of the storage medium, which is closer to the layer detected by the second detection unit, to the other side of the two surfaces of the storage medium. Therefore, the focus search can be quickly completed, and hence the reproduction of information can also be performed quickly.Type: GrantFiled: April 16, 1998Date of Patent: August 15, 2000Assignee: Pioneer Electronic CorporationInventor: Kazuki Yokota
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Patent number: 5897983Abstract: In a method for forming an annular-shaped and vertically extending bottom electrode of a memory cell capacitor, a conductive film is formed on an inter-layer insulator. A photo-resist material is applied on the conductive film to form a photo-resist film thereon. The photo-resist film is patterned by a photo-lithography using a mask which includes a transparent plate-like body and a phase shifting film selectively provided on a predetermined region of the transparent plate-like body to form an annular-shaped and vertically extending photo-resist pattern over the conductive film. The conductive film is subjected to an anisotropic etching, in which the annular-shaped and vertically extending photo-resist pattern is used as a mask, to form an annular-shaped and vertically extending bottom electrode under the annular-shaped and vertically extending photo-resist pattern. The annular-shaped and vertically extending photo-resist pattern is removed.Type: GrantFiled: May 30, 1996Date of Patent: April 27, 1999Assignee: NEC CorporationInventors: Toshiyuki Hirota, Tomomi Kurokawa, Masanobu Zenke, Kazuki Yokota
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Patent number: D911622Type: GrantFiled: February 19, 2019Date of Patent: February 23, 2021Assignee: ATOM CORPORATIONInventors: Kazuki Yokota, Toshitaka Goto
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Patent number: D997462Type: GrantFiled: November 17, 2020Date of Patent: August 29, 2023Assignee: ATOM CORPORATIONInventors: Kazuki Yokota, Toshitaka Goto