Abstract: A MOS integrated circuit comprises a semiconductor body, first and second circuit blocks formed separately on the semiconductor body, first and second power supply terminals for supplying a power voltage to the first circuit blocks, the power voltage exclusively energizing the first circuit block, third and fourth power supply terminals for supplying another power voltage to the second circuit block, the other power voltage exclusively energizing the second circuit block, the second and fourth power supply terminals being coupled through the semiconductor body, and a parallel connection of first and second diodes connected between the second and fourth power supply terminals, an anode of the first diode being connected with a cathode of the second diode and a cathode of the first diode being connected with an anode of the second diode.

Abstract: This invention provides a structure for preventing input part and/or an output part of the semiconductor chip forming complementary MOS field effect transistors from being damaged by accumulated static charges, wherein regions of the conductivity types as and higher impurity concentrations than a semiconductor substrate and a well region, respectively, are formed at the respective surfaces to come in contact with each other such that diodes be formed and the diodes are connected to an electrode pad.