Patents by Inventor Kazukiyo Joshin
Kazukiyo Joshin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9048837Abstract: A cascode transistor includes: a first switch; a second switch that has a withstand voltage higher than that of the first switch and is cascade coupled to a drain of the first switch; and a circuit in which a third switch and a capacitor are coupled in series with each other and that is provided between a connection node and a source of the first switch, the connection node being a node at which the first switch and the second switch are coupled to each other.Type: GrantFiled: September 8, 2014Date of Patent: June 2, 2015Assignee: FUJITSU LIMITEDInventors: Tatsuya Hirose, Kazukiyo Joshin
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Publication number: 20150084685Abstract: A cascode transistor includes: a first switch; a second switch that has a withstand voltage higher than that of the first switch and is cascade coupled to a drain of the first switch; and a circuit in which a third switch and a capacitor are coupled in series with each other and that is provided between a connection node and a source of the first switch, the connection node being a node at which the first switch and the second switch are coupled to each other.Type: ApplicationFiled: September 8, 2014Publication date: March 26, 2015Applicant: FUJITSU LIMITEDInventors: Tatsuya Hirose, Kazukiyo Joshin
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Patent number: 8735254Abstract: A semiconductor device has: a low concentration drain region creeping under a gate electrode of a MIS type transistor; a high concentration drain region having an impurity concentration higher than the low concentration drain region and formed in the low concentration drain region spaced apart from the gate electrode; and an opposite conductivity type region of a conductivity type opposite to the drain region formed in the low concentration drain region on a surface area between the high concentration drain region and the gate electrode, the opposite conductivity type region and low concentration drain region forming a pn junction.Type: GrantFiled: February 27, 2013Date of Patent: May 27, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Masashi Shima, Kazukiyo Joshin, Toshihide Suzuki
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Patent number: 8716748Abstract: A semiconductor device includes: a substrate; a semiconductor stacked structure, provided over the substrate, including an electron transit layer and an electron supply layer; a gate electrode, a source electrode, and a drain electrode provided over the semiconductor stacked structure; a gate pad, a source pad, and a drain pad provided over the gate electrode, the source electrode, and the drain electrode, and connected to the gate electrode, the source electrode, and the drain electrode, respectively; and a conductive layer provided under the gate pad, the source pad, and the drain pad, wherein a distance between the gate pad and the source pad is smaller than a distance between the gate pad and the drain pad.Type: GrantFiled: October 6, 2011Date of Patent: May 6, 2014Assignee: Fujitsu LimitedInventors: Tadahiro Imada, Kazukiyo Joshin
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Patent number: 8586994Abstract: A semiconductor device includes: an electron-transit layer made of a semiconductor, the electron-transit layer having a first band gap; an electron-supply layer disposed on the electron-transit layer, the electron-supply layer being made of a semiconductor having a second band gap that is wider than the first band gap; a barrier-forming layer disposed on the electron-supply layer, the barrier-forming layer being made of a semiconductor having a third band gap that is narrower than the second band gap; an upper-channel layer disposed on the barrier-forming layer, the upper-channel layer being made of a semiconductor doped with an impurity; a side-surface of the barrier-forming layer and the upper-channel layer formed by partly removing the barrier-forming layer and the upper-channel layer; an insulating-film disposed on the side-surface; a gate-electrode disposed on the insulating-film; a source-electrode connected to the upper-channel layer; and a drain-electrode connected to the electron-supply layer or theType: GrantFiled: July 26, 2012Date of Patent: November 19, 2013Assignee: Fujitsu LimitedInventor: Kazukiyo Joshin
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Patent number: 8410550Abstract: A semiconductor device has: a low concentration drain region creeping under a gate electrode of a MIS type transistor; a high concentration drain region having an impurity concentration higher than the low concentration drain region and formed in the low concentration drain region spaced apart from the gate electrode; and an opposite conductivity type region of a conductivity type opposite to the drain region formed in the low concentration drain region on a surface area between the high concentration drain region and the gate electrode, the opposite conductivity type region and low concentration drain region forming a pn junction.Type: GrantFiled: June 9, 2010Date of Patent: April 2, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Masashi Shima, Kazukiyo Joshin, Toshihide Suzuki
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Publication number: 20130056746Abstract: A semiconductor device includes: an electron-transit layer made of a semiconductor, the electron-transit layer having a first band gap; an electron-supply layer disposed on the electron-transit layer, the electron-supply layer being made of a semiconductor having a second band gap that is wider than the first band gap; a barrier-forming layer disposed on the electron-supply layer, the barrier-forming layer being made of a semiconductor having a third band gap that is narrower than the second band gap; an upper-channel layer disposed on the barrier-forming layer, the upper-channel layer being made of a semiconductor doped with an impurity; a side-surface of the barrier-forming layer and the upper-channel layer formed by partly removing the barrier-forming layer and the upper-channel layer; an insulating-film disposed on the side-surface; a gate-electrode disposed on the insulating-film; a source-electrode connected to the upper-channel layer; and a drain-electrode connected to the electron-supply layer or theType: ApplicationFiled: July 26, 2012Publication date: March 7, 2013Applicant: FUJITSU LIMITEDInventor: Kazukiyo JOSHIN
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Publication number: 20120217626Abstract: A method for manufacturing a semiconductor device, includes: placing a seal layer including a connection conductive film on the surface so that the connection conductive film is in contact with an electrode of a semiconductor element and a lead; electrically coupling the electrode and the lead through the connection conductive film; and sealing the semiconductor element by the seal layer.Type: ApplicationFiled: January 19, 2012Publication date: August 30, 2012Applicant: FUJITSU LIMITEDInventors: Taiji SAKAI, Kazukiyo Joshin, Tadahiro Imada, Nobuhiro Imaizumi, Keishiro Okamoto
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Publication number: 20120049244Abstract: A semiconductor device includes: a substrate; a semiconductor stacked structure, provided over the substrate, including an electron transit layer and an electron supply layer; a gate electrode, a source electrode, and a drain electrode provided over the semiconductor stacked structure; a gate pad, a source pad, and a drain pad provided over the gate electrode, the source electrode, and the drain electrode, and connected to the gate electrode, the source electrode, and the drain electrode, respectively; and a conductive layer provided under the gate pad, the source pad, and the drain pad, wherein a distance between the gate pad and the source pad is smaller than a distance between the gate pad and the drain pad.Type: ApplicationFiled: October 6, 2011Publication date: March 1, 2012Applicant: FUJITSU LIMITEDInventors: Tadahiro Imada, Kazukiyo Joshin
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Publication number: 20100244965Abstract: A semiconductor device has: a low concentration drain region creeping under a gate electrode of a MIS type transistor; a high concentration drain region having an impurity concentration higher than the low concentration drain region and formed in the low concentration drain region spaced apart from the gate electrode; and an opposite conductivity type region of a conductivity type opposite to the drain region formed in the low concentration drain region on a surface area between the high concentration drain region and the gate electrode, the opposite conductivity type region and low concentration drain region forming a pn junction.Type: ApplicationFiled: June 9, 2010Publication date: September 30, 2010Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Masashi Shima, Kazukiyo Joshin, Toshihide Suzuki
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Patent number: 7786487Abstract: Disclosed is a semiconductor device including a SiC substrate and a heat conductor formed in a hole in the SiC substrate and made of a linear structure of carbon elements.Type: GrantFiled: March 10, 2004Date of Patent: August 31, 2010Assignee: Fujitsu LimitedInventors: Mizuhisa Nihei, Masahiro Horibe, Yuji Awano, Kazukiyo Joshin
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Publication number: 20050067693Abstract: Disclosed is a semiconductor device including a SiC substrate and a heat conductor formed in a hole in the SiC substrate and made of a linear structure of carbon elements.Type: ApplicationFiled: March 10, 2004Publication date: March 31, 2005Applicant: FUJITSU LIMITEDInventors: Mizuhisa Nihei, Masahiro Horibe, Yuji Awano, Kazukiyo Joshin
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Patent number: 5682046Abstract: A heterojunction bipolar transistor has a support substrate, a collector layer formed on the support substrate, a base layer formed on the collector layer containing arsenic as group V element, a first emitter layer formed on the base layer, containing phosphorus as group V element, and having a band gap wider than the base layer, an emitter passivation layer formed on the first emitter layer made of semiconductor having a function of passivating the surface of the first emitter layer, and a base electrode forming an ohmic contact with the base layer. The whole upper surface of the base layer is covered with the first emitter layer and base electrode, the whole upper surface of the first emitter layer is covered with the emitter passivation layer, and the region of the first emitter layer adjacent to the edge of the base electrode is depleted throughout the full depth thereof.Type: GrantFiled: November 3, 1995Date of Patent: October 28, 1997Assignee: Fujitsu LimitedInventors: Tsuyoshi Takahashi, Hiroshi Yamada, Kazukiyo Joshin, Shigehiko Sasa