Patents by Inventor Kazukiyo Joshin

Kazukiyo Joshin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9048837
    Abstract: A cascode transistor includes: a first switch; a second switch that has a withstand voltage higher than that of the first switch and is cascade coupled to a drain of the first switch; and a circuit in which a third switch and a capacitor are coupled in series with each other and that is provided between a connection node and a source of the first switch, the connection node being a node at which the first switch and the second switch are coupled to each other.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: June 2, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Tatsuya Hirose, Kazukiyo Joshin
  • Publication number: 20150084685
    Abstract: A cascode transistor includes: a first switch; a second switch that has a withstand voltage higher than that of the first switch and is cascade coupled to a drain of the first switch; and a circuit in which a third switch and a capacitor are coupled in series with each other and that is provided between a connection node and a source of the first switch, the connection node being a node at which the first switch and the second switch are coupled to each other.
    Type: Application
    Filed: September 8, 2014
    Publication date: March 26, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Tatsuya Hirose, Kazukiyo Joshin
  • Patent number: 8735254
    Abstract: A semiconductor device has: a low concentration drain region creeping under a gate electrode of a MIS type transistor; a high concentration drain region having an impurity concentration higher than the low concentration drain region and formed in the low concentration drain region spaced apart from the gate electrode; and an opposite conductivity type region of a conductivity type opposite to the drain region formed in the low concentration drain region on a surface area between the high concentration drain region and the gate electrode, the opposite conductivity type region and low concentration drain region forming a pn junction.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: May 27, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masashi Shima, Kazukiyo Joshin, Toshihide Suzuki
  • Patent number: 8716748
    Abstract: A semiconductor device includes: a substrate; a semiconductor stacked structure, provided over the substrate, including an electron transit layer and an electron supply layer; a gate electrode, a source electrode, and a drain electrode provided over the semiconductor stacked structure; a gate pad, a source pad, and a drain pad provided over the gate electrode, the source electrode, and the drain electrode, and connected to the gate electrode, the source electrode, and the drain electrode, respectively; and a conductive layer provided under the gate pad, the source pad, and the drain pad, wherein a distance between the gate pad and the source pad is smaller than a distance between the gate pad and the drain pad.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: May 6, 2014
    Assignee: Fujitsu Limited
    Inventors: Tadahiro Imada, Kazukiyo Joshin
  • Patent number: 8586994
    Abstract: A semiconductor device includes: an electron-transit layer made of a semiconductor, the electron-transit layer having a first band gap; an electron-supply layer disposed on the electron-transit layer, the electron-supply layer being made of a semiconductor having a second band gap that is wider than the first band gap; a barrier-forming layer disposed on the electron-supply layer, the barrier-forming layer being made of a semiconductor having a third band gap that is narrower than the second band gap; an upper-channel layer disposed on the barrier-forming layer, the upper-channel layer being made of a semiconductor doped with an impurity; a side-surface of the barrier-forming layer and the upper-channel layer formed by partly removing the barrier-forming layer and the upper-channel layer; an insulating-film disposed on the side-surface; a gate-electrode disposed on the insulating-film; a source-electrode connected to the upper-channel layer; and a drain-electrode connected to the electron-supply layer or the
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: November 19, 2013
    Assignee: Fujitsu Limited
    Inventor: Kazukiyo Joshin
  • Patent number: 8410550
    Abstract: A semiconductor device has: a low concentration drain region creeping under a gate electrode of a MIS type transistor; a high concentration drain region having an impurity concentration higher than the low concentration drain region and formed in the low concentration drain region spaced apart from the gate electrode; and an opposite conductivity type region of a conductivity type opposite to the drain region formed in the low concentration drain region on a surface area between the high concentration drain region and the gate electrode, the opposite conductivity type region and low concentration drain region forming a pn junction.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: April 2, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masashi Shima, Kazukiyo Joshin, Toshihide Suzuki
  • Publication number: 20130056746
    Abstract: A semiconductor device includes: an electron-transit layer made of a semiconductor, the electron-transit layer having a first band gap; an electron-supply layer disposed on the electron-transit layer, the electron-supply layer being made of a semiconductor having a second band gap that is wider than the first band gap; a barrier-forming layer disposed on the electron-supply layer, the barrier-forming layer being made of a semiconductor having a third band gap that is narrower than the second band gap; an upper-channel layer disposed on the barrier-forming layer, the upper-channel layer being made of a semiconductor doped with an impurity; a side-surface of the barrier-forming layer and the upper-channel layer formed by partly removing the barrier-forming layer and the upper-channel layer; an insulating-film disposed on the side-surface; a gate-electrode disposed on the insulating-film; a source-electrode connected to the upper-channel layer; and a drain-electrode connected to the electron-supply layer or the
    Type: Application
    Filed: July 26, 2012
    Publication date: March 7, 2013
    Applicant: FUJITSU LIMITED
    Inventor: Kazukiyo JOSHIN
  • Publication number: 20120217626
    Abstract: A method for manufacturing a semiconductor device, includes: placing a seal layer including a connection conductive film on the surface so that the connection conductive film is in contact with an electrode of a semiconductor element and a lead; electrically coupling the electrode and the lead through the connection conductive film; and sealing the semiconductor element by the seal layer.
    Type: Application
    Filed: January 19, 2012
    Publication date: August 30, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Taiji SAKAI, Kazukiyo Joshin, Tadahiro Imada, Nobuhiro Imaizumi, Keishiro Okamoto
  • Publication number: 20120049244
    Abstract: A semiconductor device includes: a substrate; a semiconductor stacked structure, provided over the substrate, including an electron transit layer and an electron supply layer; a gate electrode, a source electrode, and a drain electrode provided over the semiconductor stacked structure; a gate pad, a source pad, and a drain pad provided over the gate electrode, the source electrode, and the drain electrode, and connected to the gate electrode, the source electrode, and the drain electrode, respectively; and a conductive layer provided under the gate pad, the source pad, and the drain pad, wherein a distance between the gate pad and the source pad is smaller than a distance between the gate pad and the drain pad.
    Type: Application
    Filed: October 6, 2011
    Publication date: March 1, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Tadahiro Imada, Kazukiyo Joshin
  • Publication number: 20100244965
    Abstract: A semiconductor device has: a low concentration drain region creeping under a gate electrode of a MIS type transistor; a high concentration drain region having an impurity concentration higher than the low concentration drain region and formed in the low concentration drain region spaced apart from the gate electrode; and an opposite conductivity type region of a conductivity type opposite to the drain region formed in the low concentration drain region on a surface area between the high concentration drain region and the gate electrode, the opposite conductivity type region and low concentration drain region forming a pn junction.
    Type: Application
    Filed: June 9, 2010
    Publication date: September 30, 2010
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Masashi Shima, Kazukiyo Joshin, Toshihide Suzuki
  • Patent number: 7786487
    Abstract: Disclosed is a semiconductor device including a SiC substrate and a heat conductor formed in a hole in the SiC substrate and made of a linear structure of carbon elements.
    Type: Grant
    Filed: March 10, 2004
    Date of Patent: August 31, 2010
    Assignee: Fujitsu Limited
    Inventors: Mizuhisa Nihei, Masahiro Horibe, Yuji Awano, Kazukiyo Joshin
  • Publication number: 20050067693
    Abstract: Disclosed is a semiconductor device including a SiC substrate and a heat conductor formed in a hole in the SiC substrate and made of a linear structure of carbon elements.
    Type: Application
    Filed: March 10, 2004
    Publication date: March 31, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Mizuhisa Nihei, Masahiro Horibe, Yuji Awano, Kazukiyo Joshin
  • Patent number: 5682046
    Abstract: A heterojunction bipolar transistor has a support substrate, a collector layer formed on the support substrate, a base layer formed on the collector layer containing arsenic as group V element, a first emitter layer formed on the base layer, containing phosphorus as group V element, and having a band gap wider than the base layer, an emitter passivation layer formed on the first emitter layer made of semiconductor having a function of passivating the surface of the first emitter layer, and a base electrode forming an ohmic contact with the base layer. The whole upper surface of the base layer is covered with the first emitter layer and base electrode, the whole upper surface of the first emitter layer is covered with the emitter passivation layer, and the region of the first emitter layer adjacent to the edge of the base electrode is depleted throughout the full depth thereof.
    Type: Grant
    Filed: November 3, 1995
    Date of Patent: October 28, 1997
    Assignee: Fujitsu Limited
    Inventors: Tsuyoshi Takahashi, Hiroshi Yamada, Kazukiyo Joshin, Shigehiko Sasa