Patents by Inventor Kazuko Hanawa

Kazuko Hanawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8492882
    Abstract: A semiconductor device has a die pad, a heat dissipating plate in the form of a frame arranged between the die pad and leads so as to surround the die pad, members that connect the die pad and the inner edge of the heat dissipating plate, and a suspension lead linked to the outer extension of the heat dissipating plate. A semiconductor chip larger than the die pad is mounted over the die pad and the members. Top surfaces of the die pad and the members in opposition to the back surface of the chip are bonded to the back surface of the chip with silver paste. Heat is conducted from the back surface of the chip to the heat dissipating plate via the silver paste, the die pad, and the members, and dissipated to the outside of the semiconductor device via the leads.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: July 23, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Junichi Arita, Kazuko Hanawa, Makoto Nishimura
  • Publication number: 20120280379
    Abstract: A semiconductor device has a die pad, a heat dissipating plate in the form of a frame arranged between the die pad and leads so as to surround the die pad, members that connect the die pad and the inner edge of the heat dissipating plate, and a suspension lead linked to the outer extension of the heat dissipating plate. A semiconductor chip larger than the die pad is mounted over the die pad and the members. Top surfaces of the die pad and the members in opposition to the back surface of the chip are bonded to the back surface of the chip with silver paste. Heat is conducted from the back surface of the chip to the heat dissipating plate via the silver paste, the die pad, and the members, and dissipated to the outside of the semiconductor device via the leads.
    Type: Application
    Filed: May 4, 2012
    Publication date: November 8, 2012
    Inventors: JUNICHI ARITA, Kazuko Hanawa, Makoto Nishimura
  • Patent number: 8188583
    Abstract: To improve the heat dissipation characteristics of a semiconductor device. The semiconductor device has a die pad, a heat dissipating plate in the form of a frame arranged between the die pad and a plurality of leads so as to surround the die pad, a plurality of members that connect the die pad and the inner edge of the heat dissipating plate, and a suspension lead linked to the outer extension of the heat dissipating plate, wherein a semiconductor chip the outer shape of which is larger than the die pad is mounted over the die pad and the members. The top surface of the die pad and the top surface of the members at the part in opposition to the back surface of the semiconductor chip are bonded to the back surface of the semiconductor chip in their entire surfaces with a silver paste.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: May 29, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Junichi Arita, Kazuko Hanawa, Makoto Nishimura
  • Publication number: 20100244214
    Abstract: To improve the heat dissipation characteristics of a semiconductor device. The semiconductor device has a die pad, a heat dissipating plate in the form of a frame arranged between the die pad and a plurality of leads so as to surround the die pad, a plurality of members that connect the die pad and the inner edge of the heat dissipating plate, and a suspension lead linked to the outer extension of the heat dissipating plate, wherein a semiconductor chip the outer shape of which is larger than the die pad is mounted over the die pad and the members. The top surface of the die pad and the top surface of the members at the part in opposition to the back surface of the semiconductor chip are bonded to the back surface of the semiconductor chip in their entire surfaces with a silver paste.
    Type: Application
    Filed: March 25, 2010
    Publication date: September 30, 2010
    Inventors: Junichi ARITA, Kazuko Hanawa, Makoto Nishimura
  • Patent number: 7804176
    Abstract: This invention is to provide a nonvolatile memory device that enhances a size reduction and mass productivity while ensuring reliability and signal transmission performance. A nonvolatile memory chip having a first side formed with no pads and a second side formed with pads is mounted on a mounting substrate. A control chip for controlling the nonvolatile memory chip is mounted on the nonvolatile memory chip. The control chip has a first pad row corresponding to the pads of the nonvolatile memory chip. The first pad row is mounted adjacent to the first side of the nonvolatile memory chip. The first pad row of the control chip and a first electrode row formed on the mounting substrate are connected via a first wire group. The pads of the nonvolatile memory chip and a second electrode row formed on the mounting substrate are connected via a second wire group. The first electrode row and the second electrode row are connected through wirings formed in the mounting substrate.
    Type: Grant
    Filed: January 23, 2007
    Date of Patent: September 28, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuko Hanawa, Takashi Kikuchi, Koichi Kanemoto, Michiaki Sugiyama, Chikako Imura
  • Publication number: 20070194454
    Abstract: This invention is to provide a nonvolatile memory device that enhances a size reduction and mass productivity while ensuring reliability and signal transmission performance. A nonvolatile memory chip having a first side formed with no pads and a second side formed with pads is mounted on a mounting substrate. A control chip for controlling the nonvolatile memory chip is mounted on the nonvolatile memory chip. The control chip has a first pad row corresponding to the pads of the nonvolatile memory chip. The first pad row is mounted adjacent to the first side of the nonvolatile memory chip. The first pad row of the control chip and a first electrode row formed on the mounting substrate are connected via a first wire group. The pads of the nonvolatile memory chip and a second electrode row formed on the mounting substrate are connected via a second wire group. The first electrode row and the second electrode row are connected through wirings formed in the mounting substrate.
    Type: Application
    Filed: January 23, 2007
    Publication date: August 23, 2007
    Inventors: Kazuko HANAWA, Takashi Kikuchi, Koichi Kanemoto, Michiaki Sugiyama, Chikako Imura