Abstract: A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Memory stack structures are formed through the vertically alternating sequence. Divider trenches and slit trenches are formed such that the divider trenches laterally extend along a first horizontal direction and divide the vertically alternating sequence into a plurality of alternating stacks of insulating layers and sacrificial material layers, and the slit trenches laterally extend along a second horizontal direction that is perpendicular to the first horizontal direction. The sacrificial material layers are replaced with electrically conductive layers employing the divider trenches as a conduit for an etchant and for a reactant. Each of the divider trenches and the slit trenches are filled with material portions to provide a plurality of divider trench fill structures in the divider trenches and to provide a plurality of slit trench fill structures in the slit trenches.

Abstract: A bonded assembly includes a memory die including a three-dimensional memory array located on a first single crystalline semiconductor substrate, and a logic die including a peripheral circuitry located on a second single crystalline semiconductor substrate and bonded to the memory die. The three-dimensional memory array includes word lines and bit lines. The logic die includes field effect transistors having semiconductor channels configured to flow electrical current along a channel direction that is parallel to the bit lines or word lines. Different crystallographic orientations are used for the first and second single crystalline semiconductor substrates. The crystallographic orientations of the first single crystalline semiconductor substrate are selected to minimize stress deformation of the memory chip, while the crystallographic orientations of the second single crystalline semiconductor substrate are selected to maximize device performance of the peripheral circuitry.

Abstract: A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Memory stack structures are formed through the vertically alternating sequence. Divider trenches and slit trenches are formed such that the divider trenches laterally extend along a first horizontal direction and divide the vertically alternating sequence into a plurality of alternating stacks of insulating layers and sacrificial material layers, and the slit trenches laterally extend along a second horizontal direction that is perpendicular to the first horizontal direction. The sacrificial material layers are replaced with electrically conductive layers employing the divider trenches as a conduit for an etchant and for a reactant. Each of the divider trenches and the slit trenches are filled with material portions to provide a plurality of divider trench fill structures in the divider trenches and to provide a plurality of slit trench fill structures in the slit trenches.

Abstract: A bonded assembly includes a memory die including a three-dimensional memory array located on a first single crystalline semiconductor substrate, and a logic die including a peripheral circuitry located on a second single crystalline semiconductor substrate and bonded to the memory die. The three-dimensional memory array includes word lines and bit lines. The logic die includes field effect transistors having semiconductor channels configured to flow electrical current along a channel direction that is parallel to the bit lines or word lines. Different crystallographic orientations are used for the first and second single crystalline semiconductor substrates. The crystallographic orientations of the first single crystalline semiconductor substrate are selected to minimize stress deformation of the memory chip, while the crystallographic orientations of the second single crystalline semiconductor substrate are selected to maximize device performance of the peripheral circuitry.

Abstract: A bonded assembly includes a memory die including a three-dimensional memory array located on a first single crystalline semiconductor substrate, and a logic die including a peripheral circuitry located on a second single crystalline semiconductor substrate and bonded to the memory die. The three-dimensional memory array includes word lines and bit lines. The logic die includes field effect transistors having semiconductor channels configured to flow electrical current along a channel direction that is parallel to the bit lines or word lines. Different crystallographic orientations are used for the first and second single crystalline semiconductor substrates. The crystallographic orientations of the first single crystalline semiconductor substrate are selected to minimize stress deformation of the memory chip, while the crystallographic orientations of the second single crystalline semiconductor substrate are selected to maximize device performance of the peripheral circuitry.

Abstract: Provided is a semiconductor device including first and second semiconductor pillars formed on a surface of a semiconductor substrate and aligning in a first direction; a first interconnect extending in a second direction intersecting with the first direction and provided between the first and second semiconductor pillars; and a first contact pad located over the first interconnect, the first contact pad being in contact with and electrically connected to the first semiconductor pillar at a side surface thereof, while being electrically isolated from the second semiconductor pillar.

Abstract: Provided is a semiconductor device including first and second semiconductor pillars formed on a surface of a semiconductor substrate and aligning in a first direction; a first interconnect extending in a second direction intersecting with the first direction and provided between the first and second semiconductor pillars; and a first contact pad located over the first interconnect, the first contact pad being in contact with and electrically connected to the first semiconductor pillar at a side surface thereof, while being electrically isolated from the second semiconductor pillar.

Abstract: Provided is a semiconductor device including first and second semiconductor pillars formed on a surface of a semiconductor substrate and aligning in a first direction; a first interconnect extending in a second direction intersecting with the first direction and provided between the first and second semiconductor pillars; and a first contact pad located over the first interconnect, the first contact pad being in contact with and electrically connected to the first semiconductor pillar at a side surface thereof, while being electrically isolated from the second semiconductor pillar.

Abstract: A method of forming a semiconductor device include the following processes. A groove is formed in a semiconductor substrate. A first insulating film is formed on a bottom surface of the groove and a second insulating film on a side surface of the groove. The second insulating film is thinner than the first insulating film. A conductive layer is formed on the first insulating film.

Abstract: Modification of an SOD film is promoted in a hot oxidizing atmosphere. Elements under a liner film and a semiconductor substrate are prevented from being damaged by oxidation. A semiconductor device includes a recess portion, a first liner film and a second liner film sequentially formed on inner wall side surfaces of the recess portion, the second liner film containing an oxygen atom, and an insulating region filled in the recess portion. The first liner film has a higher oxidation resistance than the second liner film.