Abstract: An A/D converter 11 is provided with analog input terminals 12, input terminal selection circuit 13, preset registers 15, preset data registers 16, preset data selection circuit 17, and sampling capacitor C. Input terminal selection circuit 13 selects one of analog input terminals 12. Preset registers 15 are correspondingly provided for analog input terminals 12. Preset data selection circuit 17 selects preset digital data which preset data registers 16 stores. Preset data stored at preset registers 15 corresponding to input terminals 12 designated by input terminal selection circuit 13 are converted into analog signals as pre-charge voltages. One of the preset data is selected for each analog input terminal 12 in response to kinds of the input voltages. It is supplied to sampling capacitor C as a pre-charge voltage for a sampling duration of a sampling period for the A/D conversion.

Abstract: An A/D converter 11 is provided with analog input terminals 12, input terminal selection circuit 13, preset registers 15, preset data registers 16, preset data selection circuit 17, and sampling capacitor C. Input terminal selection circuit 13 selects one of analog input terminals 12. Preset registers 15 are correspondingly provided for analog input terminals 12. Preset data selection circuit 17 selects preset digital data which preset data registers 16 stores. Preset data stored at preset registers 15 corresponding to input terminals 12 designated by input terminal selection circuit 13 are converted into analog signals as pre-charge voltages. One of the preset data is selected for each analog input terminal 12 in response to kinds of the input voltages. It is supplied to sampling capacitor C as a pre-charge voltage for a sampling duration of a sampling period for the A/D conversion.

Abstract: A voltage level shifter comprises a level changer and an output circuit. The level changer has a current block and a first transistor. A high voltage power supply higher than the potential of the low voltage power supply or the current block is connected to a source or a drain of the first transistor. The level changer outputs a potential of the high voltage power supply or a reference potential by a potential of an input signal inputted into the first transistor. The output circuit outputs an output signal having amplitude between the reference potential and the potential of the high voltage power supply when a signal from an output end of the level changer is inputted thereto.

Abstract: A programmable logic array comprises a PLA area having a plurality of banks wherein each of the bank has an array of a discharge typed logic circuit for decoding a micro-code, a command code is inputted to each bank every cycle for executing a predetermined command, and each bank outputs bank selection data for determining by which bank a command of a next cycle be decoded at the previous cycle, and a control circuit for selecting one bank for decoding the command code of the next cycle from the plurality of banks based on the bank selection data of each bank in the previous cycle, and for sending a command code to only the selected one bank to perform discharge of a discharge typed logic circuit, thereby stopping operations of other banks.

Abstract: A precharge transistor precharges a bus. A discharge transistor discharges the bus. A push-pull driver is connected to the bus, and consists of a p-channel MOS transistor and an n-channel MOS transistor. The push-pull driver sets the potential of the bus to "H" level or "L" level. A detection circuit detects which one of the discharge transistor and the push-pull driver is being driven. When the push-pull drive is being driven, a control circuit renders the precharge transistor inoperative.

Abstract: A transfer gate is made up of at least two p-channel MOS FETs and at least two n-channel MOS FETs. The current paths of the n-channel MOS FETs are connected in series, and the conduction of the FETs is controlled by a first control signal applied to the gates thereof. The current paths of the p-channel MOS FETs are also connected in series, and the conduction of the FETs is controlled by a second control signal applied to the gates thereof. The first and second control signals are opposite phase. The series circuit of the current paths of the p-channel FETs is connected in parallel to the series circuit of the current paths of the n-channel FETs. The p-channel FETs are formed in at least two n-type well regions, which is formed in the major surface region of a p-type semiconductor substrate at different locations separated from each other by predetermined distances.

Abstract: A noise cancelling circuit includes a delay circuit for delaying an input signal which is supplied to an input terminal, and a signal processing circuit responsive to the input signal and an output signal from the delay circuit, to generate an output signal corresponding to the input signal. The signal processing circuit has a first switching circuit, which includes first and second switching elements connected in series between a first power supply terminal and an output, and a second switching circuit, which includes third and fourth switching elements connected in series between a second power supply terminal and the output, wherein the first and third switching elements are responsive to the aforementioned input signal, by which they are set in mutually opposite conduction states, and the second and fourth switching elements are responsive to the output signal of the delay circuit, by which they too are set in mutually opposite conduction states.