Abstract: A random number generating circuit comprises a pseudo random number generating circuit that generates pseudo random numbers of an M-sequence; a physical random number generating circuit that generates physical random numbers; and a modulation circuit that modulates the physical random numbers generated by the physical random number generating circuit with the use of the pseudo random numbers generated by the pseudo random number generating circuit. The pseudo random number generating circuit can generate pseudo random numbers of a plurality of the M-sequences, and switches the M-sequences generated by the pseudo random number generating circuit based on the physical random numbers generated by the physical random number generating circuit.

Abstract: An encryption processing circuit which performs a permutation process of a common key block encryption system that permutes input data of plural bits according to a per-bit correspondence rule and outputs the processed data. The encryption processing circuit comprises a data input unit that receives the input data of plural bits, the data input unit having an output port that outputs the received input data of plural bits in parallel; a data output unit that has an input port to which data of plural bits is input in parallel, the data output unit outputting the data of plural bits inputted to the input port; and a permuting unit that connects the output port and the input port according to the per-bit correspondence rule.

Abstract: A keyless entry system comprising a transmitter and a receiver. The transmitter increases a first number stored in the volatile memory according to rules, and transmits the first number by radio. The receiver receives the first number, and if the first number is greater than a second number stored in a memory, outputs a signal to indicate being authenticated as correct and updates the second number to the first number. Further, each time increase in the first number becomes a multiple of a predetermined number, the transmitter writes into a non-volatile memory a third number equal to the predetermined number plus the first number. When the first number in the volatile memory is erased due to the exchange, etc., of the battery, the transmitter reads out the third number from the non-volatile memory and writes the third number as the first number into the volatile memory.

Abstract: A selection circuit causes either a memory 6H or 6L to enter an enabled state according to address data A16 of address data A0-A16 when a mode signal M is 1. The selection circuit comprises OR gates (10, 12) which output different outputs. When the address data A16 is 0, a nonvolatile memory 6L enters an enabled state. Then, the memory 6L is addressed according to the address data A0-A15 so that, for example, 8-bit lower data is written therein. On the other hand, when the address data A16 is 1, a nonvolatile memory 6H becomes in an enabled state. Then, the memory 6H is addressed according to the address data A0-A15 so that, for example, 8-bit upper data is written therein. Also, when an external terminal (17) is grounded, and a mode signal become 0, the OR gates (10, 12) outputs signals 0, so that the memories 6H, 6L simultaneously become in an enabled state. When data is read from corresponding addresses of each memory, data of, for example, 16-bits is obtained.

Abstract: When writing of data into nonvolatile memories 8H and 8L is started, data D7 and D15 corresponding to the 128th word of a data input section 8B are inverted and outputted. When accurate writing is subsequently performed, the data D7 and D15 are outputted as they are. By monitoring a change of the data D7 and D15 from the nonvolatile memories 8H and 8L, it is possible to detect whether writing is still continuing or has already completed. Thus, by using nonvolatile memories of 8 bit data width or the like, a 16-bit microcomputer can be easily realized.

Abstract: Control data indicating the vertical start positions of display characters is written into the locations of a video RAM determined by a common column address and a plurality of column addresses. In each horizontal synchronizing period, all control data is read in sequence from the video RAM and set in sequence in a vertical start position register. A match is found between the contents of the vertical position counter indicating the current vertical position and the contents of the vertical start position register. When they match, after the horizontal synchronizing period, the video RAM is accessed with the control data as the vertical position start address.

Abstract: A clock signal generator comprising a first oscillator which normally supplies clock pulses to the output of the clock signal generator, a first counter for counting the pulses generated from the first oscillator and producing a carry signal after counting n1 pulses generated from the first oscillator, a second oscillator for producing clock pulses for possible back-up purpose, a second counter for counting the pulses generated from the second oscillator and adapted to produce a carry signal after counting n2 pulses generated from the second oscillator and to be reset by the carry signal from the first counter, n2 being larger than n1, and a control circuit which blocks the output from the second oscillator as long as no carry signal is supplied thereto from the second oscillator.