Patents by Inventor Kazumasa Hiramatsu

Kazumasa Hiramatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8053811
    Abstract: A group 3-5 nitride semiconductor multilayer substrate (1) and a method for manufacturing such substrate are provided. A semiconductor layer (12) is formed on a base substrate (11), and a mask (13) is formed on the semiconductor layer (12). Then, after forming a group 3-5 nitride semiconductor crystalline layer (14) by selective growing, the group 3-5 nitride semiconductor crystalline layer (14) and the base substrate (11) are separated. The crystallinity of the semiconductor layer (12) is lower than that of the group 3-5 nitride semiconductor crystalline layer (14).
    Type: Grant
    Filed: May 2, 2006
    Date of Patent: November 8, 2011
    Assignees: Sumitomo Chemical Company Limited, National University Corporation Mie University
    Inventors: Kazumasa Hiramatsu, Hideto Miyake, Yoshihiko Tsuchida, Yoshinobu Ono, Naohiro Nishikawa
  • Publication number: 20090085165
    Abstract: A group 3-5 nitride semiconductor multilayer substrate (1) and a method for manufacturing such substrate are provided. A semiconductor layer (12) is formed on a base substrate (11), and a mask (13) is formed on the semiconductor layer (12). Then, after forming a group 3-5 nitride semiconductor crystalline layer (14) by selective growing, the group 3-5 nitride semiconductor crystalline layer (14) and the base substrate (11) are separated. The crystallinity of the semiconductor layer (12) is lower than that of the group 3-5 nitride semiconductor crystalline layer (14).
    Type: Application
    Filed: May 2, 2006
    Publication date: April 2, 2009
    Applicants: SUMITOMO CHEMICAL COMPANY, LIMITED, National University Corporation Mie University
    Inventors: Kazumasa Hiramatsu, Hideto Miyake, Yoshihiko Tsuchida, Yoshinobu Ono, Naohiro Nishikawa
  • Patent number: 7399687
    Abstract: The present invention relates to a method for producing an epitaxial substrate having a III-V group compound semiconductor crystal represented by the general formula InxGayAlzN (wherein, x+y+z=1, 0?x?1, 0?y?1, 0?z?1) having reduced dislocation density, comprising a first step of covering with a mask made of a different material from the III-V group compound semiconductor so that only portions around points of the crystal constitute openings by using a III-V group compound semiconductor crystal having a plurality of projection shapes and a second step of growing the III-V group compound semiconductor crystal laterally by using the III-V group compound semiconductor crystal at the opening as a seed crystal. According to the present invention, an epitaxial substrate having a III-V group compound semiconductor crystal having low dislocation density and little warp is obtained.
    Type: Grant
    Filed: March 4, 2004
    Date of Patent: July 15, 2008
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Kazumasa Hiramatsu, Hideto Miyake, Shinya Bohyama, Takayoshi Maeda, Yoshinobu Ono
  • Publication number: 20060172512
    Abstract: The present invention relates to a method for producing an epitaxial substrate having a III-V group compound semiconductor crystal represented by the general formula InxGayAlzN (wherein, x+y+z=1, 0?x?1, 0?y?1, 0?z?1) having reduced dislocation density, comprising a first step of covering with a mask made of a different material from the III-V group compound semiconductor so that only portions around points of the crystal constitute openings by using a III-V group compound semiconductor crystal having a plurality of projection shapes and a second step of growing the III-V group compound semiconductor crystal laterally by using the III-V group compound semiconductor crystal at the opening as a seed crystal. According to the present invention, an epitaxial substrate having a III-V group compound semiconductor crystal having low dislocation density and little warp is obtained.
    Type: Application
    Filed: March 4, 2004
    Publication date: August 3, 2006
    Inventors: Kazumasa Hiramatsu, Hideto Miyake, Shinya Bohyama, Takayoshi Maeda, Yoshinobu Ono
  • Patent number: 6946308
    Abstract: When a crystal layer of III-V Group nitride compound semiconductor is formed, a nitride compound semiconductor layer is first overlaid on a substrate to form a base layer and a III-V Group nitride compound semiconductor represented by the general formula InxGayAlzN (where 0?x?1, 0?y?1, 0?z?1, x+y+z=1) is epitaxially grown on the base layer by hydride vapor phase epitaxy at a deposition pressure of not lower than 800 Torr. By making the deposition pressure not lower than 800 Torr, the crystallinity of the III-V Group nitride compound semiconductor can be markedly improved and its defect density reduced.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: September 20, 2005
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Kazumasa Hiramatsu, Hideto Miyake, Shinya Bohyama, Takayoshi Maeda, Yasushi Iyechika
  • Patent number: 6844574
    Abstract: Provided is a III-V compound semiconductor having a layer formed from a first III-V compound semiconductor expressed by the general formula InuGavAlwN (where 0?u?1, 0?v?1, 0?w?1, u+v+w=1), a pattern formed on the layer from a material different not only from the first III-V compound semiconductor but also from a second III-V compound semiconductor hereinafter described, and a layer formed on the first III-V compound semiconductor and the pattern from the second III-V compound semiconductor expressed by the general formula InxGayAlzN (where 0?x?1, 0?y?1, 0?x?1, x+y+z=1), wherein the full width at half maximum of the (0004) reflection X-ray rocking curve of the second III-V compound semiconductor is 700 seconds or less regardless of the direction of X-ray incidence. In the III-V compound semiconductor, which is a high quality semiconductor, the occurrence of low angle grain boundaries is suppressed.
    Type: Grant
    Filed: March 10, 2000
    Date of Patent: January 18, 2005
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Kazumasa Hiramatsu, Hideto Miyake, Takayoshi Maeda, Yasushi Iyechika
  • Publication number: 20040157358
    Abstract: A group III nitride semiconductor film involving few lattice defects and having a large thickness, and a process for making the film are disclosed. Dry-etching is conducted while a quartz substrate and a group III nitride semiconductor are placed on the top of a lower electrode. Nano-pillars (50) are formed on the top of the group III nitride semiconductor (101). Another group III nitride semiconductor film (51) is deposited on the nano-pillars (50).
    Type: Application
    Filed: April 1, 2004
    Publication date: August 12, 2004
    Inventors: Kazumasa Hiramatsu, Hideto Miyake, Harumasa Yoshida, Tatsuhiro Urushido, Yusuke Terada
  • Patent number: 6756246
    Abstract: A method for fabricating a GaN-based III-V Group compound semiconductor is provided that utilizes a regrowth method based on the HVPE method to form a second III-V Group compound semiconductor layer having a flat surface on a first III-V Group compound semiconductor layer formed with a mask layer. The method uses a mixed carrier gas of hydrogen gas and nitrogen gas to control formation of a facet group including at least the {33-62} facet by the regrowth, and conducting the regrowth until a plane parallel to the surface of the first III-V Group compound semiconductor layer is once annihilated, thereby fabricating a III-V Group compound semiconductor having low dislocation density.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: June 29, 2004
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Kazumasa Hiramatsu, Hideto Miyake, Shinya Bohyama, Takayoshi Maeda, Yasushi Iyechika
  • Patent number: 6734515
    Abstract: A semiconductor light receiving element having a light receiving layer (1) formed from a GaN group semiconductor, and an electrode (2) formed on one surface of the light receiving layer as a light receiving surface (1a) in such a way that the light (L) can enter the light receiving layer is provided. When the light receiving element is of a Schottky barrier type, the aforementioned electrode (2) contains at least a Schottky electrode, which is formed in such a way that, on the light receiving surface (1a), the total length of the boundary lines between areas covered with the Schottky electrode and exposed areas is longer than the length of the outer periphery of the light receiving surface (1a).
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: May 11, 2004
    Assignees: Mitsubishi Cable Industries, Ltd., Nikon Corporation
    Inventors: Kazuyuki Tadatomo, Hiroaki Okagawa, Youichiro Ohuchi, Masahiro Koto, Kazumasa Hiramatsu, Yutaka Hamamura, Sumito Shimizu
  • Publication number: 20030211710
    Abstract: When a crystal layer of III-V Group nitride compound semiconductor is formed, a nitride compound semiconductor layer is first overlaid on a substrate to form a base layer and a III-V Group nitride compound semiconductor represented by the general formula InxGayAlzN (where 0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1) is epitaxially grown on the base layer by hydride vapor phase epitaxy at a deposition pressure of not lower than 800 Torr. By making the deposition pressure not lower than 800 Torr, the crystallinity of the III-V Group nitride compound semiconductor can be markedly improved and its defect density reduced.
    Type: Application
    Filed: March 26, 2003
    Publication date: November 13, 2003
    Inventors: Kazumasa Hiramatsu, Hideto Miyake, Shinya Bohyama, Takayoshi Maeda, Yasushi Iyechika
  • Publication number: 20030045017
    Abstract: A method for fabricating a GaN-based III-V Group compound semiconductor is provided that utilizes a regrowth method based on the HVPE method to form a second III-V Group compound semiconductor layer having a flat surface on a first III-V Group compound semiconductor layer formed with a mask layer. The method uses a mixed carrier gas of hydrogen gas and nitrogen gas to control formation of a facet group including at least the {33-62} facet by the regrowth, and conducting the regrowth until a plane parallel to the surface of the first III-V Group compound semiconductor layer is once annihilated, thereby fabricating a III-V Group compound semiconductor having low dislocation density.
    Type: Application
    Filed: March 26, 2002
    Publication date: March 6, 2003
    Inventors: Kazumasa Hiramatsu, Hideto Miyake, Shinya Bohyama, Takayoshi Maeda, Yasushi Iyechika
  • Patent number: 6503610
    Abstract: Provided is a method of producing a group III-V compound semiconductor having a low dislocation density without increasing the thickness of a re-grown layer, the method includes a re-growing process using a mask pattern, and threading dislocations in the re-grown layer are terminated by the voids formed on the pattern.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: January 7, 2003
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Kazumasa Hiramatsu, Hideto Miyake, Takayoshi Maeda, Yasushi Iyechika
  • Publication number: 20010031385
    Abstract: Provided is a method of producing a group III-V compound semiconductor having a low dislocation density without increasing the thickness of a re-grown layer, the method includes a re-growing process using a mask pattern, and threading dislocations in the re-grown layer are terminated by the voids formed on the pattern.
    Type: Application
    Filed: March 23, 2001
    Publication date: October 18, 2001
    Inventors: Kazumasa Hiramatsu, Hideto Miyake, Takayoshi Maeda, Yasushi Iyechika
  • Patent number: 6225650
    Abstract: A GaN group crystal base member comprising a base substrate, a mask layer partially covering the surface of said base substrate to give a masked region, and a GaN group crystal layer grown thereon to cover the mask layer, which is partially in direct contact with the non-masked region of the base substrate, use thereof for a semiconductor element, manufacturing methods thereof and a method for controlling a dislocation line. The manufacturing method of the present invention is capable of making a part in the GaN group crystal layer, which is above a masked region or non-masked region, have a low dislocation density.
    Type: Grant
    Filed: March 24, 1998
    Date of Patent: May 1, 2001
    Assignee: Mitsubishi Cable Industries, Ltd.
    Inventors: Kazuyuki Tadatomo, Hiroaki Okagawa, Youichiro Ohuchi, Keiji Miyashita, Kazumasa Hiramatsu, Nobuhiko Sawaki, Katsunori Yahashi, Takumi Shibata
  • Patent number: 5846844
    Abstract: A nitrogen-group III compound semiconductor satisfying the formula Al.sub.x Ga.sub.y In.sub.1-x-y N, inclusive of x=0, y=0 and x=y=0, and a method for producing the same comprising the steps of forming a zinc oxide (ZnO) intermediate layer on a sapphire substrate, forming a nitrogen-group III semiconductor layer satisfying the formula Al.sub.x Ga.sub.y In.sub.1-x-y N, inclusive of x=0, y=0 and x=y=0 on the intermediate ZnO layer, and separating the intermediate ZnO layer by wet etching with an etching liquid only for the ZnO layer.
    Type: Grant
    Filed: February 7, 1996
    Date of Patent: December 8, 1998
    Assignees: Toyoda Gosei Co., Ltd., Isamu Akasaki, Hiroshi Amano, Kazumasa Hiramatsu
    Inventors: Isamu Akasaki, Hiroshi Amano, Kazumasa Hiramatsu, Theeradetch Detchprohm
  • Patent number: 5810925
    Abstract: A GaN single crystal having a full width at half-maximum of the double-crystal X-ray rocking curve of 5-250 sec and a thickness of not less than 80 .mu.m, a method for producing the GaN single crystal having superior quality and sufficient thickness permitting its use as a substrate and a semiconductor light emitting element having high luminance and high reliability, comprising, as a substrate, the GaN single crystal having superior quality and/or sufficient thickness permitting its use as a substrate.
    Type: Grant
    Filed: May 17, 1996
    Date of Patent: September 22, 1998
    Assignee: Mitsubishi Cable Industries, Ltd.
    Inventors: Kazuyuki Tadatomo, Shinichi Watabe, Hiroaki Okagawa, Kazumasa Hiramatsu
  • Patent number: 5770887
    Abstract: A GaN single crystal having a full width at half-maximum of the double-crystal X-ray rocking curve of 5-250 sec and a thickness of not less than 80 .mu.m, a method for producing the GaN single crystal having superior quality and sufficient thickness permitting its use as a substrate and a semiconductor light emitting element having high luminance and high reliability, comprising, as a substrate, the GaN single crystal having superior quality and/or sufficient thickness permitting its use as a substrate.
    Type: Grant
    Filed: October 11, 1994
    Date of Patent: June 23, 1998
    Assignee: Mitsubishi Cable Industries, Ltd.
    Inventors: Kazuyuki Tadatomo, Shinichi Watabe, Hiroaki Okagawa, Kazumasa Hiramatsu
  • Patent number: 5370738
    Abstract: A compound semiconductor vapor phase epitaxial device comprises a cylindrical reactor vessel, a plurality of flow channels disposed in the reactor vessel, a crystal substrate disposed in one of the flow channels, a plurality of gas supply pipes for respectively supplying gas containing element of compound to be grown on the crystal substrate and at least one slit or linearly arranged fine holes communicating adjacent two flow channels so as to extend in a direction normal to a direction of the gas flow to form a laminate layer flow consisting of two or more than two gases at an upstream portion of location of the crystal substrate.
    Type: Grant
    Filed: February 3, 1993
    Date of Patent: December 6, 1994
    Assignees: Pioneer Electronic Corporation, Hiroshi Amano, Isamu Akasaki
    Inventors: Atsushi Watanabe, Hiroshi Amano, Kazumasa Hiramatsu, Isamu Akasaki
  • Patent number: 5218216
    Abstract: A thin film of SiO.sub.2 is patterned on an N layer consisting of N-type Al.sub.x Ga.sub.1-x N (inclusive of x=0). Next, I-type Al.sub.x Ga.sub.1-x N (inclusive of x=0) is selectively grown and the portion on the N layer grows into an I-layer consisting an active layer of a light emitting diode, and that on the SiO.sub.2 thin film grows into a conductive layer. Electrodes are formed on the I-layer and conductive layer to constitute the light emitting diode. Also, on the surface a ({1120}) of a sapphire substrate, a buffer layer consisting of aluminum nitride is formed, onto which a gallium nitride group semiconductor is formed.
    Type: Grant
    Filed: December 20, 1991
    Date of Patent: June 8, 1993
    Assignees: Toyoda Gosei Co., Ltd., Nagoya University
    Inventors: Katsuhide Manabe, Nobuo Okazaki, Isamu Akasaki, Kazumasa Hiramatsu, Hiroshi Amano
  • Patent number: 5122845
    Abstract: A substrate for producing a gallium nitride compound-semiconductor (Al.su Ga.sub.1-x N; X=0 inclusive) device in vapor phase on a sapphire substrate using gaseous organometallic compound, and a also blue light emitting diode produced by using the substrate. The buffer layer comprising aluminium nitride (AlN) and having a crystal structure where microcrystal or polycrystal is mixed in amorphous state, is formed on the sapphire substrate. The buffer layer is formed at a growth temperature of 380.degree. to 800.degree. C. to have a thickness of 100 to 500 .ANG.. Further, on the buffer layer is formed the layer of gallium nitride compound-semiconductor (Al.sub.x Ga.sub.1-x N; X=0 inclusive). The layer of gallium nitride compound-semiconductor (Al.sub.x Ga.sub.1-x N; X=0 inclusive) comprising at least two layers having different conductive types and being sequentially layered on the buffer layer, functions as a light emitting layer.
    Type: Grant
    Filed: February 26, 1990
    Date of Patent: June 16, 1992
    Assignees: Toyoda Gosei Co., Ltd., Nagoya University and Research Development Corporation of Japan
    Inventors: Katsuhide Manabe, Hisaki Kato, Isamu Akasaki, Kazumasa Hiramatsu, Hiroshi Amano