Patents by Inventor Kazumasa Kido
Kazumasa Kido has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10896892Abstract: Provided is a wire bonding apparatus for electrically connecting an electrode and an aluminum alloy wire to each other by wire bonding. The apparatus includes a wire feeding device which feeds the wire. The wire has a diameter not less than 500 ?m and not greater than 600 ?m. The apparatus includes a heating device heats the wire to a temperature that is not lower than 50° C. and not higher than 100° C. The apparatus further includes a pressure device which presses the wire against the electrode. The apparatus further includes an ultrasonic wave generating device which generates an ultrasonic vibration that is applied to the wire that is pressed by the pressure device.Type: GrantFiled: March 9, 2015Date of Patent: January 19, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventors: Fumihiko Momose, Takashi Saito, Kazumasa Kido, Yoshitaka Nishimura
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Patent number: 10157877Abstract: A solder joint layer has a structure in which plural fine-grained second crystal sections (22) precipitate at crystal grain boundaries between first crystal sections (21) dispersed in a matrix. The first crystal sections (21) are Sn crystal grains containing tin and antimony in a predetermined proportion. The second crystal sections (22) are made up of a first portion containing a predetermined proportion of Ag atoms with respect to Sn atoms, or a second portion containing a predetermined proportion of Cu atoms with respect to Sn atoms, or both. The solder joint layer may have third crystal sections (23) which are crystal grains that contain a predetermined proportion of Sb atoms with respect to Sn atoms. As a result, solder joining is enabled at a low melting point, and a highly reliable solder joint layer having a substantially uniform metal structure can be formed.Type: GrantFiled: October 8, 2015Date of Patent: December 18, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Kazumasa Kido, Takashi Saitou, Kyouhei Fukuda, Shinji Tada, Fumihiko Momose, Yoshitaka Nishimura
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Patent number: 9978701Abstract: A highly reliable semiconductor device capable of heavy current conduction and high temperature operation has a module structure in which a semiconductor chip and a circuit pattern are electrically connected via a wire. A front surface metal film is formed on a front surface electrode of the chip, and the wire is bonded to the front surface metal film by wire bonding. The chip has a front surface electrode on the front surface of an Si substrate or an SiC substrate, and has a rear surface substrate on the rear surface thereof. The front surface metal film is a Ni film or a Ni alloy film of having a thickness ranging from 3 ?m to 7 ?m. The wire is an Al wire having an increased recrystallizing temperature and improved strength due to controlling the crystal grain sizes before wire bonding to a range of 1 ?m to 20 ?m.Type: GrantFiled: September 3, 2015Date of Patent: May 22, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Takashi Saito, Fumihiko Momose, Kazumasa Kido, Yoshitaka Nishimura
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Patent number: 9748186Abstract: A semiconductor device has a module structure in which a semiconductor element and a circuit layer are electrically connected to each other by a wire. A front metal layer is formed on a surface of a top side electrode of the semiconductor element and the wire is bonded to the front metal layer by wire bonding. The front metal layer has a higher hardness than the top side electrode or the wire. A bonding interface of the wire with the metal film has a recrystallization temperature that is equal to or higher than 175° C. According to this structure, it is possible to improve the power cycle resistance of the semiconductor device.Type: GrantFiled: September 3, 2015Date of Patent: August 29, 2017Assignee: FUJI ELECTRIC CO., LTD.Inventors: Fumihiko Momose, Takashi Saito, Kazumasa Kido, Yoshitaka Nishimura
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Publication number: 20160035683Abstract: A highly reliable semiconductor device capable of heavy current conduction and high temperature operation has a module structure in which a semiconductor chip and a circuit pattern are electrically connected via a wire. A front surface metal film is formed on a front surface electrode of the chip, and the wire is bonded to the front surface metal film by wire bonding. The chip has a front surface electrode on the front surface of an Si substrate or an SiC substrate, and has a rear surface substrate on the rear surface thereof. The front surface metal film is a Ni film or a Ni alloy film of having a thickness ranging from 3 ?m to 7 ?m. The wire is an Al wire having an increased recrystallizing temperature and improved strength due to controlling the crystal grain sizes before wire bonding to a range of 1 ?m to 20 ?m.Type: ApplicationFiled: September 3, 2015Publication date: February 4, 2016Applicant: FUJI ELECTRIC CO., LTD.Inventors: Takashi SAITO, Fumihiko MOMOSE, Kazumasa KIDO, Yoshitaka NISHIMURA
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Publication number: 20160035690Abstract: A solder joint layer has a structure in which plural fine-grained second crystal sections (22) precipitate at crystal grain boundaries between first crystal sections (21) dispersed in a matrix. The first crystal sections (21) are Sn crystal grains containing tin and antimony in a predetermined proportion. The second crystal sections (22) are made up of a first portion containing a predetermined proportion of Ag atoms with respect to Sn atoms, or a second portion containing a predetermined proportion of Cu atoms with respect to Sn atoms, or both. The solder joint layer may have third crystal sections (23) which are crystal grains that contain a predetermined proportion of Sb atoms with respect to Sn atoms. As a result, solder joining is enabled at a low melting point, and a highly reliable solder joint layer having a substantially uniform metal structure can be formed.Type: ApplicationFiled: October 8, 2015Publication date: February 4, 2016Applicant: FUJI ELECTRIC CO., LTD.Inventors: Kazumasa KIDO, Takashi SAITOU, Kyouhei FUKUDA, Shinji TADA, Fumihiko MOMOSE, Yoshitaka NISHIMURA
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Publication number: 20150380368Abstract: A semiconductor device has a module structure in which a semiconductor element and a circuit layer are electrically connected to each other by a wire. A front metal layer is formed on a surface of a top side electrode of the semiconductor element and the wire is bonded to the front metal layer by wire bonding. The front metal layer has a higher hardness than the top side electrode or the wire. A bonding interface of the wire with the metal film has a recrystallization temperature that is equal to or higher than 175° C. According to this structure, it is possible to improve the power cycle resistance of the semiconductor device.Type: ApplicationFiled: September 3, 2015Publication date: December 31, 2015Applicant: FUJI ELECTRIC CO., LTD.Inventors: Fumihiko MOMOSE, Takashi SAITO, Kazumasa KIDO, Yoshitaka NISHIMURA
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Publication number: 20150303166Abstract: Provided is a wire bonding apparatus for electrically connecting an electrode and an aluminum alloy wire to each other by wire bonding. The apparatus includes a wire feeding device which feeds the wire. The wire has a diameter not less than 500 ?m and not greater than 600 ?m. The apparatus includes a heating device heats the wire to a temperature that is not lower than 50° C. and not higher than 100° C. The apparatus further includes a pressure device which presses the wire against the electrode. The apparatus further includes an ultrasonic wave generating device which generates an ultrasonic vibration that is applied to the wire that is pressed by the pressure device.Type: ApplicationFiled: March 9, 2015Publication date: October 22, 2015Applicant: FUJI ELECTRIC CO., LTD.Inventors: Fumihiko MOMOSE, Takashi SAITO, Kazumasa KIDO, Yoshitaka NISHIMURA
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Patent number: 8860220Abstract: An ultrasonic welding tool is used to bond end portions of an external connection terminal to circuit patterns of an insulating substrate, with a Vickers hardness not lower than 90. Bonding end portions are provided integrally with a bar in the external connection terminal. A bonding end portion located substantially in the lengthwise center of the bar is bonded first, then others are bonded alternately in order toward either end. Hardness of the bonding end portions is increased so that strength of the ultrasonic welding portions is increased, and displacement of the bonding end portion in either end from its regular position is suppressed to keep bonding strength high. Bonding strength of the ultrasonic welding portions between the external connection terminal and the circuit patterns of the insulating substrate can be increased so that long-term reliability can be secured in a semiconductor device.Type: GrantFiled: February 8, 2013Date of Patent: October 14, 2014Assignee: Fuji Electric Co., Ltd.Inventors: Fumihiko Momose, Kazumasa Kido, Yoshitaka Nishimura, Fumio Shigeta
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Publication number: 20130244380Abstract: An ultrasonic welding tool is used to bond end portions of an external connection terminal to circuit patterns of an insulating substrate, with a Vickers hardness not lower than 90. Bonding end portions are provided integrally with a bar in the external connection terminal. A bonding end portion located substantially in the lengthwise center of the bar is bonded first, then others are bonded alternately in order toward either end. Hardness of the bonding end portions is increased so that strength of the ultrasonic welding portions is increased, and displacement of the bonding end portion in either end from its regular position is suppressed to keep bonding strength high. Bonding strength of the ultrasonic welding portions between the external connection terminal and the circuit patterns of the insulating substrate can be increased so that long-term reliability can be secured in a semiconductor device.Type: ApplicationFiled: February 8, 2013Publication date: September 19, 2013Applicant: FUJI ELECTRIC CO., LTD.Inventors: Fumihiko MOMOSE, Kazumasa KIDO, Yoshitaka NISHIMURA, Fumio SHIGETA
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Patent number: 8395262Abstract: Hardness of bonding end portions of an external connection terminal to be bonded to circuit patterns of an insulating substrate which is not lower than 90 in Vickers hardness is disclosed. An ultrasonic welding tool is used. In the external connection terminal in which the bonding end portions are provided integrally with a bar, one of the bonding end portion located substantially in the lengthwise center of the bar is first bonded, and the other bonding end portions are bonded alternately in order toward either end. The hardness of the bonding end portions is increased so that strength of the ultrasonic welding portions is increased.Type: GrantFiled: September 10, 2010Date of Patent: March 12, 2013Assignee: Fuji Electric Co., Ltd.Inventors: Fumihiko Momose, Kazumasa Kido, Yoshitaka Nishimura, Fumio Shigeta
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Publication number: 20110186999Abstract: Hardness of bonding end portions of an external connection terminal to be bonded to circuit patterns of an insulating substrate which is not lower than 90 in Vickers hardness is disclosed. An ultrasonic welding tool is used. In the external connection terminal in which the bonding end portions are provided integrally with a bar, one of the bonding end portion located substantially in the lengthwise center of the bar is first bonded, and the other bonding end portions are bonded alternately in order toward either end. The hardness of the bonding end portions is increased so that strength of the ultrasonic welding portions is increased.Type: ApplicationFiled: September 10, 2010Publication date: August 4, 2011Applicant: FUJI ELECTRIC SYSTEMS CO., LTD.Inventors: Fumihiko Momose, Kazumasa Kido, Yoshitaka Nishimura, Fumio Shigeta