Patents by Inventor Kazumasa Kioi

Kazumasa Kioi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240150309
    Abstract: An object of the present invention is to provide a compound having an anti-inflammatory activity or a pharmacologically acceptable salt thereof. The solution of the present invention is a compound of general formula (1) or a pharmacologically acceptable salt thereof. wherein the symbols in the formula are defined below: R1: e.g., a C1-C6 alkyl group; R2: a C1-C6 alkyl group; A: e.g., an oxygen atom; and R3: e.g., a C1-C6 alkyl group.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 9, 2024
    Applicant: Daiichi Sankyo Company, Limited
    Inventors: Keiji Saito, Katsuyoshi Nakajima, Toru Taniguchi, Osamu Iwamoto, Satoshi Shibuya, Yasuyuki Ogawa, Kazumasa Aoki, Nobuya Kurikawa, Shinji Tanaka, Momoko Ogitani, Eriko Kioi, Kaori Ito, Natsumi Nishihama, Tsuyoshi Mikkaichi, Wataru Saitoh
  • Patent number: 8194806
    Abstract: This demodulation device receives and demodulates a digital broadcast wave. This demodulation device includes an RF search control unit (41) and a GI search control unit (42). The RF search control unit (41) determines whether or not there is a broadcast wave in a certain channel, in accordance with an intensity of a signal outputted from a tuner (12) for receiving a digital broadcast wave. The GI search control unit (42) determines whether or not the broadcast wave is digital, based on whether or not the signal outputted from the tuner (12) contains a guard interval. Thus, the demodulation device is capable of efficiently searching for a channel containing a digital broadcast wave.
    Type: Grant
    Filed: July 5, 2007
    Date of Patent: June 5, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Mamoru Okazaki, Kazumasa Kioi, Akira Saito, Masayuki Natsumi, Atsushi Sakai
  • Patent number: 7881672
    Abstract: A digital demodulating apparatus comprises a tuner constituted by circuit elements to perform channel select processing to a signal; a demodulator that performs demodulation processing to a signal output from the tuner; a power supply unit that supplies a normal power to each circuit element, and supplies to the circuit element a test power different from the normal power, over a first time period in place of the normal power; a test noise measuring unit that measures the intensity of test noise contained in a signal to be output from the tuner, when the power supply unit supplies the test power over the first time period; a comparing unit that compares the intensity of the test noise measured by the test noise measuring unit with a noise reference value as a reference for updating of the normal power; and a power updating unit that updates the intensity of the normal power on the basis of a result of the comparison by the comparing unit.
    Type: Grant
    Filed: January 18, 2007
    Date of Patent: February 1, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Nobuyoshi Kaiki, Takae Sakai, Masayuki Natsumi, Kazumasa Kioi
  • Publication number: 20100202552
    Abstract: In a case where there are a plurality of spurious disturbing waves, each of which has a strong peak at a particular frequency, in a transmission band, correlation between the disturbing waves becomes nonconstant so that it becomes difficult to remove the correlation between the disturbing waves. An OFDM demodulator of the present invention includes a symbol integration circuit (131) for integrating a guard correlation signal in a symbol number direction, and an offset removal circuit (132) for removing an offset from the guard correlation signal integrated in the symbol number direction. An amplitude component due to the disturbing wave, which amplitude component is included in the guard correlation signal, is cancelled by the integration in the symbol number direction, so that it is possible to successfully remove the offset from the guard correlation signal.
    Type: Application
    Filed: May 14, 2008
    Publication date: August 12, 2010
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Atsushi Sakai, Arnaud Santraine, Akira Saito, Masayuki Natsumi, Mamoru Okazaki, Kazumasa Kioi
  • Publication number: 20090268856
    Abstract: This demodulation device receives and demodulates a digital broadcast wave. This demodulation device includes an RF search control unit (41) and a GI search control unit (42). The RF search control unit (41) determines whether or not there is a broadcast wave in a certain channel, in accordance with an intensity of a signal outputted from a tuner (12) for receiving a digital broadcast wave. The GI search control unit (42) determines whether or not the broadcast wave is digital, based on whether or not the signal outputted from the tuner (12) contains a guard interval. Thus, the demodulation device is capable of efficiently searching for a channel containing a digital broadcast wave.
    Type: Application
    Filed: July 5, 2007
    Publication date: October 29, 2009
    Inventors: Mamoru Okazaki, Kazumasa Kioi, Akira Saito, Masayuki Natsumi, Atsushi Sakai
  • Publication number: 20070275680
    Abstract: A digital demodulating apparatus comprises a tuner constituted by circuit elements to perform channel select processing to a signal; a demodulator that performs demodulation processing to a signal output from the tuner; a power supply unit that supplies a normal power to each circuit element, and supplies to the circuit element a test power different from the normal power, over a first time period in place of the normal power; a test noise measuring unit that measures the intensity of test noise contained in a signal to be output from the tuner, when the power supply unit supplies the test power over the first time period; a comparing unit that compares the intensity of the test noise measured by the test noise measuring unit with a noise reference value as a reference for updating of the normal power; and a power updating unit that updates the intensity of the normal power on the basis of a result of the comparison by the comparing unit.
    Type: Application
    Filed: January 18, 2007
    Publication date: November 29, 2007
    Inventors: Nobuyoshi Kaiki, Takae Sakai, Masayuki Natsumi, Kazumasa Kioi
  • Patent number: 6009021
    Abstract: A MOS logic circuit is charged by adiabatic charging, and is composed of a clamp circuit having a pair of PMOS transistors, and two functional circuits, each having at least one NMOS transistor, a gate electrode of each of the NMOS transistors being an input node, one terminal of each functional circuit being connected to a common constant-voltage power source, and the other terminal of each functional circuit being connected to a drain electrode of the corresponding PMOS transistor, thus forming an output node. A substrate electrode of each of the NMOS transistors making up the two functional circuits is cross-connected to the output node of the other functional circuit. In this way, even in the HOLD operation, in which both input nodes fall to low level, the NMOS transistor which is to output low level becomes depletion mode, and the outputting operations are stabilized without increasing circuit size.
    Type: Grant
    Filed: October 23, 1997
    Date of Patent: December 28, 1999
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Kazumasa Kioi
  • Patent number: 5956755
    Abstract: A switching circuit supplies a signal from a write memory selection terminal and its inverted signal to one of a first or a second selector and the other of the first or the second selector according to an output signal from a forward/backward translation selection terminal. In a forward translation process, the first and second selectors select a translated address on a translated address bus in a writing stage and select an input address on an input address bus in a reading stage. In a backward translation process, the selectors select the input address in the writing stage and select the translated address in the reading stage. Consequently, the forward translation and the backward translation are executed using the same translation table. An address translation table memory therefore stores therein only either a translation table for forward translation or a translation table for backward translation.
    Type: Grant
    Filed: April 11, 1997
    Date of Patent: September 21, 1999
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Youji Kanie, Kazumasa Kioi
  • Patent number: 5144395
    Abstract: An optically driven semiconductor device is disclosed which comprises a semiconductor substrate, a plurality of vertical field effect transistors formed on the substrate, and a plurality of optoelectric transducers formed on an insulating film above the respective transistors, wherein the transistors have the substrate in common as a drain. Also disclosed is an optically driven semiconductor device which comprises a semiconductor substrate, a vertical field effect transistor formed on the substrate and a solar cell formed on an insulating film above the substrate, wherein the solar cell is formed with a polycrystalline silicon layer or monocrystalline silicon layer grown by the chemical vapor deposition method. Moreover, there are disclosed optically coupled semiconductor relay devices using these optically driven semiconductor devices.
    Type: Grant
    Filed: March 19, 1991
    Date of Patent: September 1, 1992
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshiaki Miyajima, Kazumasa Kioi, Mituo Matunami, Tukasa Doi, Minoru Yoshioka, Masayoshi Koba