Patents by Inventor Kazumasa Kishimoto

Kazumasa Kishimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11870212
    Abstract: A mesa (34) includes a resonator and a second conductivity type contact layer (24). Grooves (32) are provided on both sides of the mesa (34). The first conductivity type contact layer (12) and a side face of the mesa (34) including an end face of the resonator construct an L shape (50). The first conductivity type contact layer (12) constructs bottom surfaces of the L shape (50) and the grooves (32). A side face of the groove (32) includes a slope (38) near the bottom surface (46) and a side face (42) above. A side face of the L shape (50) includes a slope (40) near the bottom surface (48) and a side face (44) above. A first electrode (28) is connected to the first conductivity type contact layer (12) at the bottom surface (46) of the groove (32). A second electrode (30) is connected to the second conductivity type contact layer (24) above the mesa (34).
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: January 9, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazumasa Kishimoto, Naoki Nakamura
  • Publication number: 20220416511
    Abstract: A laminate (22) is formed on a semiconductor substrate (10). Two or more grooves (54) are formed in the laminate (22). A mesa (24) with two grooves among the two or more grooves (54) positioned on both sides is formed. An insulating resin film (30) is embedded into the two or more grooves (54). A first opening (32) is formed at the insulating resin film (30) embedded in one of the two or more grooves (54) and an electrode (46) extracted upward from a bottom surface (36) is formed. A first side surface (34) of the insulating resin film (30) is inclined in a forward tapered direction.
    Type: Application
    Filed: March 16, 2020
    Publication date: December 29, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Motoshi KITAGAWA, Kazumasa KISHIMOTO
  • Patent number: 11456576
    Abstract: A method for manufacturing an optical semiconductor device having a ridge stripe configuration containing an active layer and current blocking layers which embed both sides of the ridge stripe configuration, comprises steps of forming a mask of an insulating film on a surface of a semiconductor layer containing an active layer, forming a ridge stripe configuration by etching a semiconductor layer using gas containing SiCl4, removing an oxide layer with regard to a Si based residue which is attached on a surface which is etched of the ridge stripe configuration which is formed and removing a Si based residue whose oxide layer is removed.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: September 27, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hitoshi Sakuma, Kazumasa Kishimoto
  • Publication number: 20210119418
    Abstract: A method for manufacturing an optical semiconductor device having a ridge stripe configuration containing an active layer and current blocking layers which embed both sides of the ridge stripe configuration, comprises steps of forming a mask of an insulating film on a surface of a semiconductor layer containing an active layer, forming a ridge stripe configuration by etching a semiconductor layer using gas containing SiCl4, removing an oxide layer with regard to a Si based residue which is attached on a surface which is etched of the ridge stripe configuration which is formed and removing a Si based residue whose oxide layer is removed.
    Type: Application
    Filed: July 13, 2020
    Publication date: April 22, 2021
    Applicant: Mitsubishi Electric Corporation
    Inventors: Hitoshi SAKUMA, Kazumasa KISHIMOTO
  • Publication number: 20200350741
    Abstract: A mesa (34) includes a resonator and a second conductivity type contact layer (24). Grooves (32) are provided on both sides of the mesa (34). The first conductivity type contact layer (12) and a side face of the mesa (34) including an end face of the resonator construct an L shape (50). The first conductivity type contact layer (12) constructs bottom surfaces of the L shape (50) and the grooves (32). A side face of the groove (32) includes a slope (38) near the bottom surface (46) and a side face (42) above. A side face of the L shape (50) includes a slope (40) near the bottom surface (48) and a side face (44) above. A first electrode (28) is connected to the first conductivity type contact layer (12) at the bottom surface (46) of the groove (32). A second electrode (30) is connected to the second conductivity type contact layer (24) above the mesa (34).
    Type: Application
    Filed: March 28, 2018
    Publication date: November 5, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kazumasa KISHIMOTO, Naoki NAKAMURA
  • Patent number: 9184566
    Abstract: A method for manufacturing a semiconductor laser element includes forming an etching end point detection layer on part of a substrate, forming an substrate exposed portion and forming a lower cladding layer, an active layer, and an upper cladding layer on the etching end point detection layer and on the exposed portion, forming an insulating film pattern at a distance corresponding to a clearance region, from directly above a boundary between the substrate exposed portion and the etching end point detection layer, etching the upper clad layer, the active layer, and the lower cladding layer using the insulating film pattern as a mask and stopping etching at a time when the etching end point detection layer is exposed or after a predetermined time duration after the time.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: November 10, 2015
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Kazumasa Kishimoto
  • Publication number: 20150180198
    Abstract: A method for manufacturing a semiconductor laser element includes forming an etching end point detection layer on part of a substrate, forming an substrate exposed portion and forming a lower cladding layer, an active layer, and an upper cladding layer on the etching end point detection layer and on the exposed portion, forming an insulating film pattern at a distance corresponding to a clearance region, from directly above a boundary between the substrate exposed portion and the etching end point detection layer, etching the upper clad layer, the active layer, and the lower cladding layer using the insulating film pattern as a mask and stopping etching at a time when the etching end point detection layer is exposed or after a predetermined time duration after the time.
    Type: Application
    Filed: November 3, 2014
    Publication date: June 25, 2015
    Inventor: Kazumasa Kishimoto