Patents by Inventor Kazumasa Kohama

Kazumasa Kohama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5731607
    Abstract: In a semiconductor integrated circuit device, particularly in a switch circuit, a first and a second FETs are connected in series with respect to the signal path, and a third FET is connected between the node of these first and second FETs and the ground region. Thereby, low insertion loss, high isolation, and miniaturization of the entire circuit can be realized simultaneously.
    Type: Grant
    Filed: April 17, 1996
    Date of Patent: March 24, 1998
    Assignee: Sony Corporation
    Inventor: Kazumasa Kohama
  • Patent number: 5717356
    Abstract: A switching circuit further decreasing the insertion loss. The first capacitor is connected between the drain terminal of the field effect transistor and the ground and/or the second capacitor is connected between the source terminal of the field effect transistor and the ground, and the capacitances of the first and/or second capacitors are set to optimum values. Accordingly, the switching circuit can be easily obtained which is low in insertion loss at a desired frequency. Besides, since a bias circuit for generating bias voltage from control voltage which is applied to the two control terminals of a switching circuit using a field effect transistor is provided, a switching circuit which does not need exclusive bias terminals and is superior in isolation property can be realized.
    Type: Grant
    Filed: January 23, 1996
    Date of Patent: February 10, 1998
    Assignee: Sony Corporation
    Inventor: Kazumasa Kohama
  • Patent number: 5548239
    Abstract: A radio receiver-transmitter apparatus equipped with a signal changeover switch which is capable of properly dealing with a high-power radio frequency signal and ensuring a desired insertion loss and superior isolation characteristic. The switch has a signal input terminal, a signal output terminal and a signal input-output terminal, and comprises a 1st FET unit connected to the input terminal and the input-output terminal, a 2nd FET unit connected to the input terminal and the ground, a 3rd FET unit connected to the output terminal and the input-output terminal, and a 4th FET unit connected to the output terminal and the ground.
    Type: Grant
    Filed: May 10, 1994
    Date of Patent: August 20, 1996
    Assignee: Sony Corporation
    Inventor: Kazumasa Kohama
  • Patent number: 5448207
    Abstract: An attenuator circuit which has a small insertion loss and also has a broad tolerance toward the fluctuation of the element parameter. An attenuator stage having the largest attenuation quantity of a plurality of attenuator stages is formed with a .pi.-type attenuator stage, and an attenuator stage having the smallest attenuation quantity of the plurality of attenuator stages is formed with a T-type attenuator stage. In this way, an attenuator stage having a large attenuation quantity whose precision of the attenuation quantity is apt to be detracted is formed with a .pi.-type attenuator stage so that the precision becomes high, further, an attenuator stage having a small attenuation quantity is formed with a T-type attenuator stage so that the insertion loss can be lowered.
    Type: Grant
    Filed: September 14, 1994
    Date of Patent: September 5, 1995
    Assignee: Sony Corporation
    Inventor: Kazumasa Kohama