Abstract: A semiconductor device including an input terminal to receive an input signal and an output terminal to output an output signal includes delay elements connected in series with the input terminal and each to assign the delay to the input signal input from the input terminal, selectors connected to output sides of the delay elements and each to select one of output signals of the delay elements based on a selection signal for selecting the one of the output signals of the delay elements to return the selected one of the output signals to the output terminal, and delay circuits disposed corresponding to the selectors and each to cause switching of the selection signal input into a corresponding one of the selectors to occur after switching of a signal level of the input signal input into the corresponding one of the selectors serving as a signal turning point.

Abstract: A semiconductor device includes a delay part configured to assign a delay to an input signal, a phase detector configured to detect a phase of an output signal output from the delay part, a setting part configured to set a stable operations range of the phase of the output signal based on phase information output from the phase detector, and an error detector configured to set an acceptable range corresponding to the stable operations range, determine whether a phase of the output signal falls within the acceptable range, and change the acceptable range based on an extraneous factor of an input signal of the delay part.

Abstract: A semiconductor apparatus includes a delay circuit to apply delay to an input signal, a phase detector to detect a phase of an output signal which is outputted from the delay circuit, a filter to set a range of the phase of the output signal for stable operation based on phase information outputted from the phase detector, a counter to count a number of detections of the output signal when the phase deviates from the range for stable operation, a discount controller to generate a discount signal indicating a discount number for the number counted by the counter, in accordance with an operating condition or an external factor outside the delay circuit and an error detector to determine whether or not an error of the phase of the output signal has occurred based on the number counted by the counter and a discount number indicated by the discount signal.

Abstract: Plural unit delay circuits connected in series and an output circuit that non-inverts or inverts and outputs an output signal in accordance with a set signal are included. A first unit delay circuit includes a selector that outputs a signal input to a second input terminal when the set signal is “0”, and outputs a signal input to a first input terminal when the set signal is “1”, and an inverter that inverts and outputs an output of the selector from a second output terminal. A second unit delay circuit includes an inverter that inverts the signal input to the first input terminal and outputs from a first output terminal, and a selector that outputs the signal input to the second input terminal when the set signal is “0”, and outputs an output of the inverter when the set signal is “1” from the second output terminal.

Abstract: A semiconductor device includes a delay part configured to assign a delay to an input signal, a phase detector configured to detect a phase of an output signal output from the delay part, a setting part configured to set a stable operations range of the phase of the output signal based on phase information output from the phase detector, and an error detector configured to set an acceptable range corresponding to the stable operations range, determine whether a phase of the output signal falls within the acceptable range, and change the acceptable range based on an extraneous factor of an input signal of the delay part.

Abstract: Plural unit delay circuits connected in series and an output circuit that non-inverts or inverts and outputs an output signal in accordance with a set signal are included. A first unit delay circuit includes a selector that outputs a signal input to a second input terminal when the set signal is “0”, and outputs a signal input to a first input terminal when the set signal is “1”, and an inverter that inverts and outputs an output of the selector from a second output terminal. A second unit delay circuit includes an inverter that inverts the signal input to the first input terminal and outputs from a first output terminal, and a selector that outputs the signal input to the second input terminal when the set signal is “0”, and outputs an output of the inverter when the set signal is “1” from the second output terminal.

Abstract: In a semiconductor device, a selector selects a different reference voltage depending on whether the impedance of a transmitter or of a receiver is to be adjusted, and causes a reference voltage generator to generate the selected reference voltage. The reference voltage generator generates the reference voltage selected by the selector and applies the generated reference voltage to an impedance adjuster. The impedance adjuster adjusts the impedance of the transmitter and the impedance of the receiver, separately from each other, in accordance with the input reference voltage.

Abstract: A semiconductor device including an input terminal to receive an input signal and an output terminal to output an output signal includes delay elements connected in series with the input terminal and each to assign the delay to the input signal input from the input terminal, selectors connected to output sides of the delay elements and each to select one of output signals of the delay elements based on a selection signal for selecting the one of the output signals of the delay elements to return the selected one of the output signals to the output terminal, and delay circuits disposed corresponding to the selectors and each to cause switching of the selection signal input into a corresponding one of the selectors to occur after switching of a signal level of the input signal input into the corresponding one of the selectors serving as a signal turning point.

Abstract: A semiconductor apparatus includes a delay circuit to apply delay to an input signal, a phase detector to detect a phase of an output signal which is outputted from the delay circuit, a filter to set a range of the phase of the output signal for stable operation based on phase information outputted from the phase detector, a counter to count a number of detections of the output signal when the phase deviates from the range for stable operation, a discount controller to generate a discount signal indicating a discount number for the number counted by the counter, in accordance with an operating condition or an external factor outside the delay circuit and an error detector to determine whether or not an error of the phase of the output signal has occurred based on the number counted by the counter and a discount number indicated by the discount signal.

Abstract: In a semiconductor device, a selector selects a different reference voltage depending on whether the impedance of a transmitter or of a receiver is to be adjusted, and causes a reference voltage generator to generate the selected reference voltage. The reference voltage generator generates the reference voltage selected by the selector and applies the generated reference voltage to an impedance adjuster. The impedance adjuster adjusts the impedance of the transmitter and the impedance of the receiver, separately from each other, in accordance with the input reference voltage.

Abstract: The present invention relates to the selected-wavelength tuning apparatus which is provided with an AOTF, a radio-frequency signal generator, an optical detector, and a controller for detecting lights emitted from the AOTF with the optical detector and for controlling a frequency of the radio-frequency generator so as to detect a light of predetermined wavelength.