Patents by Inventor Kazumasa Nishio

Kazumasa Nishio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230343702
    Abstract: An electronic component includes a chip that has a main surface, an insulating layer that is laminated at a thickness exceeding 2200 nm on the main surface and has a first end on the chip side and a second end on an opposite side to the chip, and a resistive film that is arranged inside the insulating layer such as not to be positioned within a thickness range of less than 2200 nm on a basis of the first end and includes an alloy crystal constituted of a metal element and a nonmetal element.
    Type: Application
    Filed: July 6, 2023
    Publication date: October 26, 2023
    Applicant: ROHM CO., LTD.
    Inventors: Bungo TANAKA, Kazumasa NISHIO
  • Patent number: 9673144
    Abstract: A semiconductor device has a resistor area and wiring area selectively disposed on a semiconductor substrate. In this semiconductor device, a second interlayer insulating film is formed above the semiconductor substrate, and a thin-film resistor is disposed on the second interlayer insulating film in the resistor area. Vias that contact the thin-film resistor from below are formed in the second interlayer insulating film. A wiring line is disposed on the second interlayer insulating film in the wiring area. A dummy wiring line that covers the thin-film resistor from above is disposed in a third wiring layer that is in the same layer as the wiring line, and an insulating film is interposed between the thin-film resistor and the dummy wiring line.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: June 6, 2017
    Assignee: ROHM CO., LTD.
    Inventors: Isamu Nishimura, Michihiko Mifuji, Kazumasa Nishio
  • Patent number: 9511402
    Abstract: The invention enhances a cooling effect on a press die for hot press. A lower die includes a first base, a second base mounted on the first base and having an opening in the center, a support table provided in the opening of the second base, and a die portion detachably mounted on the support table and including die pieces. The die portion is divided in die pieces disposed adjoining each other, and cold water pipes are provided in the die pieces respectively. The cold water pipes are bent in a U shape and inserted in the die pieces respectively, and extended downward from the lower ends of the die pieces respectively. The cold water pipes have cooling water injection ends and cooling water ejection ends in a space between the first base and the support table.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: December 6, 2016
    Assignee: TOA Industries Co., Ltd.
    Inventors: Koji Hayashi, Taichi Shimizu, Kazumasa Nishio
  • Publication number: 20160111365
    Abstract: A semiconductor device has a resistor area and wiring area selectively disposed on a semiconductor substrate. In this semiconductor device, a second interlayer insulating film is formed above the semiconductor substrate, and a thin-film resistor is disposed on the second interlayer insulating film in the resistor area. Vias that contact the thin-film resistor from below are formed in the second interlayer insulating film. A wiring line is disposed on the second interlayer insulating film in the wiring area. A dummy wiring line that covers the thin-film resistor from above is disposed in a third wiring layer that is in the same layer as the wiring line, and an insulating film is interposed between the thin-film resistor and the dummy wiring line.
    Type: Application
    Filed: December 21, 2015
    Publication date: April 21, 2016
    Applicant: ROHM CO., LTD.
    Inventors: lsamu Nishimura, Michihiko Mifuji, Kazumasa Nishio
  • Patent number: 9257387
    Abstract: A semiconductor device has a resistor area and wiring area selectively disposed on a semiconductor substrate. In this semiconductor device, a second interlayer insulating film is formed above the semiconductor substrate, and a thin-film resistor is disposed on the second interlayer insulating film in the resistor area. Vias that contact the thin-film resistor from below are formed in the second interlayer insulating film. A wiring line is disposed on the second interlayer insulating film in the wiring area. A dummy wiring line that covers the thin-film resistor from above is disposed in a third wiring layer that is in the same layer as the wiring line, and an insulating film is interposed between the thin-film resistor and the dummy wiring line.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: February 9, 2016
    Assignee: ROHM CO., LTD.
    Inventors: Isamu Nishimura, Michihiko Mifuji, Kazumasa Nishio
  • Publication number: 20150348900
    Abstract: A semiconductor device has a resistor area and wiring area selectively disposed on a semiconductor substrate. In this semiconductor device, a second interlayer insulating film is formed above the semiconductor substrate, and a thin-film resistor is disposed on the second interlayer insulating film in the resistor area. Vias that contact the thin-film resistor from below are formed in the second interlayer insulating film. A wiring line is disposed on the second interlayer insulating film in the wiring area. A dummy wiring line that covers the thin-film resistor from above is disposed in a third wiring layer that is in the same layer as the wiring line, and an insulating film is interposed between the thin-film resistor and the dummy wiring line.
    Type: Application
    Filed: August 12, 2015
    Publication date: December 3, 2015
    Applicant: ROHM CO., LTD.
    Inventors: lsamu Nishimura, Michihiko Mifuji, Kazumasa Nishio
  • Patent number: 9136216
    Abstract: A semiconductor device has a resistor area and wiring area selectively disposed on a semiconductor substrate. In this semiconductor device, a second interlayer insulating film is formed above the semiconductor substrate, and a thin-film resistor is disposed on the second interlayer insulating film in the resistor area. Vias that contact the thin-film resistor from below are formed in the second interlayer insulating film. A wiring line is disposed on the second interlayer insulating film in the wiring area. A dummy wiring line that covers the thin-film resistor from above is disposed in a third wiring layer that is in the same layer as the wiring line, and an insulating film is interposed between the thin-film resistor and the dummy wiring line.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: September 15, 2015
    Assignee: ROHM CO., LTD.
    Inventors: Isamu Nishimura, Michihiko Mifuji, Kazumasa Nishio
  • Publication number: 20140239445
    Abstract: A semiconductor device has a resistor area and wiring area selectively disposed on a semiconductor substrate. In this semiconductor device, a second interlayer insulating film is formed above the semiconductor substrate, and a thin-film resistor is disposed on the second interlayer insulating film in the resistor area. Vias that contact the thin-film resistor from below are formed in the second interlayer insulating film. A wiring line is disposed on the second interlayer insulating film in the wiring area. A dummy wiring line that covers the thin-film resistor from above is disposed in a third wiring layer that is in the same layer as the wiring line, and an insulating film is interposed between the thin-film resistor and the dummy wiring line.
    Type: Application
    Filed: February 14, 2014
    Publication date: August 28, 2014
    Applicant: ROHM CO., LTD.
    Inventors: lsamu Nishimura, Michihiko Mifuji, Kazumasa Nishio
  • Publication number: 20140157854
    Abstract: The invention enhances a cooling effect on a press die for hot press. A lower die includes a first base, a second base mounted on the first base and having an opening in the center, a support table provided in the opening of the second base, and a die portion detachably mounted on the support table and including die pieces. The die portion is divided in die pieces disposed adjoining each other, and cold water pipes are provided in the die pieces respectively. The cold water pipes are bent in a U shape and inserted in the die pieces respectively, and extended downward from the lower ends of the die pieces respectively. The cold water pipes have cooling water injection ends and cooling water ejection ends in a space between the first base and the support table.
    Type: Application
    Filed: March 13, 2013
    Publication date: June 12, 2014
    Inventors: Koji HAYASHI, Taichi SHIMIZU, Kazumasa NISHIO
  • Patent number: 6528177
    Abstract: An object of the present invention is to provide a cladding material, which has high joining strength and excellent productivity, and a manufacturing method therefor; in order to attain this object, the present invention provides a cladding material comprising: a first material to be joined which is made of aluminum or an aluminum alloy; a second material to be joined which is made of a single metal or an alloy and which is join the first material to be joined; and an intermediate layer which is provided between the first and second materials to be joined.
    Type: Grant
    Filed: October 29, 2001
    Date of Patent: March 4, 2003
    Assignees: Mitsubishi Heavy Industries, Ltd.
    Inventors: Takayuki Kawano, Yoshiaki Inoue, Katsuaki Inoue, Kawaichi Katsumi, Hiroshi Iwabuchi, Kazumasa Nishio, Shizuo Mukae, Masahiro Hirata
  • Publication number: 20020168540
    Abstract: An object of the present invention is to provide a cladding material, which has high joining strength and excellent productivity, and a manufacturing method therefor; in order to attain this object, the present invention provides a cladding material comprising: a first material to be joined which is made of aluminum or an aluminum alloy; a second material to be joined which is made of a single metal or an alloy and which is join the first material to be joined; and an intermediate layer which is provided between the first and second materials to be joined.
    Type: Application
    Filed: October 29, 2001
    Publication date: November 14, 2002
    Inventors: Takayuki Kawano, Yoshiaki Inoue, Katsuaki Inoue, Kawaichi Katsumi, Hiroshi Iwabuchi, Kazumasa Nishio, Shizuo Mukae, Masahiro Hirata