Abstract: An error flag processor for digital signals includes a memory having an information word frame comprised of signal words and correction words, an error detector for detecting errors in an input signal in units of one frame, a write address circuit for writing into an error flag RAM one error flag for one frame upon detection of an error in the words of the frame, an error correcting circuit for correcting data subjected to de-interleave and a read out of the memory, and read address circuit for reading error flags in units of one frame corresponding to individual words from the memory to the error correcting circuit, whereby the storage requirements for the error flags can be reduced. When old storage regions for correction words in the information word frame memory are used as error flag regions and the error flags are arranged in accordance with the signal word frames, the error flag RAM can be omitted.