Abstract: A controller, which is installed on a power supply device complying with the USB (Universal Serial Bus)-PD (power delivery) specification and controls a power supply circuit for supplying a bus voltage to a power receiving device via a bus line is disclosed. The controller includes an interface circuit, which communicates with the power supply device via the bus line; a processor, which transmits and receives messages to and from the power receiving device by using the interface circuit, determines a voltage level of the bus voltage, and sets the determined voltage level to the power supply circuit; and a watchdog timer, which is cleared whenever the processor executes a ping-related command for transmission or reception of ping messages to or from the power receiving device, wherein an overflow period of the watchdog timer is set to be longer than a period for the ping messages.

Abstract: A controller, which is installed on a power supply device complying with the USB (Universal Serial Bus)-PD (power delivery) specification and controls a power supply circuit for supplying a bus voltage to a power receiving device via a bus line is disclosed. The controller includes an interface circuit, which communicates with the power supply device via the bus line; a processor, which transmits and receives messages to and from the power receiving device by using the interface circuit, determines a voltage level of the bus voltage, and sets the determined voltage level to the power supply circuit; and a watchdog timer, which is cleared whenever the processor executes a ping-related command for transmission or reception of ping messages to or from the power receiving device, wherein an overflow period of the watchdog timer is set to be longer than a period for the ping messages.

Abstract: A microcomputer or microcontroller with a watchdog timer-counter also has an external reset signal generator. When the central processing unit of the microcomputer or microcontroller fails to execute its control program correctly, the watchdog timer-counter generates an internal reset signal for a first interval, resetting the central processing unit, and the external reset signal generator generates an external reset signal for a second interval, different from the first interval. The length of the second interval can be set to match the requirements of external peripheral devices to which the external reset signal is supplied.

Abstract: The present invention provides an LSI which comprises first circuit areas (e.g., an I/O area and a VBAT area) in which power is always held ON, a second circuit area (e.g., a CORE area) capable of ON/OFF-switching of the power, a power control circuit which is provided within the corresponding first circuit area and outputs a control signal for performing power control on the second circuit area, and a reset signal detection circuit which is provided within the corresponding first circuit area and detects an internal standby reset signal or an external standby reset signal to control the operation of the power control circuit.

Abstract: A semiconductor integrated circuit includes a bridge circuit which controls a data transfer of a bus line, peripheral circuits which are connected to the bridge circuit through the bus line, and a control circuit which is formed at the peripheral circuits. The control circuit receives a select signal and controls the data transfer in the peripheral circuits in accordance with a logic state of the select signal.

Abstract: A semiconductor integrated circuit includes a bridge circuit which controls a data transfer of a bus line, peripheral circuits which are connected to the bridge circuit through the busline, and a control circuit which is formed at the peripheral circuits. The control circuit receives a select signal and controls the data transfer in the peripheral circuits in accordance with a logic state of the select signal.

Abstract: A semiconductor integrated circuit includes a bridge circuit which controls a data transfer of a bus line, peripheral circuits which are connected to the bridge circuit through the busline, and a control circuit which is formed at the peripheral circuits. The control circuit receives a select signal and controls the data transfer in the peripheral circuits in accordance with a logic state of the select signal.

Abstract: The present invention provides an LSI which comprises first circuit areas (e.g., an I/O area and a VBAT area) in which power is always held ON, a second circuit area (e.g., a CORE area) capable of ON/OFF-switching of the power, a power control circuit which is provided within the corresponding first circuit area and outputs a control signal for performing power control on the second circuit area, and a reset signal detection circuit which is provided within the corresponding first circuit area and detects an internal standby reset signal or an external standby reset signal to control the operation of the power control circuit.

Abstract: A circuit which generates a dot clock synchronized to an external video signal which can ensure a pulse width allowed by a device which is supplied with the dot clock. A high frequency clock is divided to generate a first dot clock, and the phase is initialized in accordance with information on a previously set frequency division ratio upon detection of a significant edge of a horizontal synchronization signal. Also, a second dot clock, the logical level of which changes every minimum allowable period, is formed from the high frequency clock in accordance with information on a previously set minimum allowable period, and the phase is modified upon detection of the significant edge such that the minimum allowable period is ensured for the logical level period even before and after the detection.

Abstract: A semiconductor integrated circuit includes a bridge circuit which controls a data transfer of a bus line, peripheral circuits which are connected to the bridge circuit through the busline, and a control circuit which is formed at the peripheral circuits. The control circuit receives a select signal and controls the data transfer in the peripheral circuits in accordance with a logic state of the select signal.

Abstract: A semiconductor integrated circuit that allows a self test of an integrated circuit built into a system to be conducted through a circuit structure on a smaller scale and achieves an improvement in the accuracy of the self test is provided. An integrated circuit includes functional modules respectively provided with built-in self testing circuits and a self test control circuit that individually controls the built-in self testing circuits. This structure allows self tests to be automatically performed within the integrated circuit without requiring external components. The scale of the system having the built-in integrated circuit may thus be reduced. Also, by building up the built-in self testing circuits in the individual functional modules to a sufficient degree, a high-quality self test comparable to that conducted prior to shipment can be performed even after the integrated circuit is built into the system.

Abstract: A microcomputer or microcontroller with a watchdog timer-counter also has an external reset signal generator. When the central processing unit of the microcomputer or microcontroller fails to execute its control program correctly, the watchdog timer-counter generates an internal reset signal for a first interval, resetting the central processing unit, and the external reset signal generator generates an external reset signal for a second interval, different from the first interval. The length of the second interval can be set to match the requirements of external peripheral devices to which the external reset signal is supplied.

Abstract: A circuit which generates a dot clock synchronized to an external video signal which can ensure a pulse width allowed by a device which is supplied with the dot clock. A high frequency clock is divided to generate a first dot clock, and the phase is initialized in accordance with information on a previously set frequency division ratio upon detection of a significant edge of a horizontal synchronization signal. Also, a second dot clock, the logical level of which changes every minimum allowable period, is formed from the high frequency clock in accordance with information on a previously set minimum allowable period, and the phase is modified upon detection of the significant edge such that the minimum allowable period is ensured for the logical level period even before and after the detection.

Abstract: A semiconductor integrated circuit includes a bridge circuit which controls a data transfer of a bus line, peripheral circuits which are connected to the bridge circuit through the busline, and a control circuit which is formed at the peripheral circuits. The control circuit receives a select signal and controls the data transfer in the peripheral circuits in accordance with a logic state of the select signal.

Abstract: A semiconductor integrated circuit includes a bridge circuit which controls a data transfer of a bus line, peripheral circuits which are connected to the bridge circuit through the bus line, and a control circuit which is formed at the peripheral circuits. The control circuit receives a select signal and controls the data transfer in the peripheral circuits in accordance with a logic state of the select signal.

Abstract: A semiconductor integrated circuit includes a bridge circuit which controls a data transfer of a bus line, peripheral circuits which are connected to the bridge circuit through the busline, and a control circuit which is formed at the peripheral circuits. The control circuit receives a select signal and controls the data transfer in the peripheral circuits in accordance with a logic state of the select signal.

Abstract: A timer apparatus which can simultaneously control the operations of a plurality of timers without adjusting the operation of a counter of each timer in a software manner is provided. The same address information is added to an operation command to the counter of each timer (20, 30, 40, . . . , 90), so the operation commands to the counters are simultaneously written into registers synchronously with a clock. Thus, the timing to start or stop the operations of the counters of the timers (20, 30, 40, . . . , 90) can be made to coincide.

Abstract: Predetermined programs and data are written into a first flash memory. The first flash memory is divided into a plurality of blocks. Security information for the respective blocks of the first flash memory is written into a second flash memory. The security information indicates whether or not reading of the stored data to the outside from the respective blocks of the first flash memory is prohibited. When a read target address signal is output by a CPU, the corresponding read data is read from the first flash memory and supplied to the CPU and a tri-state buffer. As a result, the CPU is able to obtain desired input data. A security signal from the second flash memory is supplied to the control terminal of the tri-state buffer. Accordingly, if reading of data to the outside is prohibited, the read data is not transmitted to the outside.

Abstract: Predetermined programs and data are written into a first flash memory. The first flash memory is divided into a plurality of blocks. Security information for the respective blocks of the first flash memory is written into a second flash memory. The security information indicates whether or not reading of the stored data to the outside from the respective blocks of the first flash memory is prohibited. When a read target address signal is output by a CPU, the corresponding read data is read from the first flash memory and supplied to the CPU and a tri-state buffer. As a result, the CPU is able to obtain desired input data. A security signal from the second flash memory is supplied to the control terminal of the tri-state buffer. Accordingly, if reading of data to the outside is prohibited, the read data is not transmitted to the outside.

Abstract: A semiconductor integrated circuit that allows a self test of a semiconductor integrated circuit built into a system to be conducted through a circuit structure on a smaller scale and achieves an improvement in the accuracy of the self test is provided. A semiconductor integrated circuit 100 comprises functional modules 104, 105 and 106 respectively provided with built-in self testing circuits and a self test control circuit 102 that individually controls the built-in self testing circuits. This structure allows self tests to be automatically performed within the semiconductor integrated circuit without requiring any external components. As a result, the scale of the system having the built-in semiconductor integrated circuit can be reduced.