Abstract: The present invention provides a semiconductor device which is excellent in voltage sense characteristic and simple in manufacturing process. P diffusion regions 12 and 13 are selectively formed on a first major surface of an N.sup.- substrate 11, an electrode 31 is formed on the P diffusion region, a sense electrode 32 is formed on the P diffusion region 13, and an electrode 33 is formed on a second major surface of the N.sup.- substrate. Then, the electrode 31 is set at 0 V, constant current is led to the sense electrode 32, and the electrode 33 is positively biased. Thus, the voltage applied to the electrode 33 is sensed from a potential obtained at the sense electrode 32. A distance between the P diffusion regions 12 and 13 which determines a voltage sense characteristic can be accurately controlled, and a good voltage sense characteristic can be obtained. Moreover, a manufacturing process is relatively simple.

Abstract: There are provided a plurality of standard cell blocks (2) within an IC chip (1), and an aluminium wiring layer is formed in an aluminium wiring region (8) provided between the standard cell blocks (2) to electrically connect the standard cell blocks (2) to each other. An n-type epitaxial region (4), a p-type diffusion region (5) and an n-type diffusion region (6) are incorporated in an underlayer of the aluminium wiring region (8), to thereby form an evaluation device which is an npn bipolar transistor under the aluminium wiring region (8). A semiconductor device which is capable of accurately evaluating its finished product by the inspection of the evaluation device is provided without the damage of an integration level.

Abstract: The present invention relates to a semiconductor device which is fabricated in simple process steps and which prevents deterioration in a breakdown voltage. Two diffusion regions are formed in space in a surface of an n.sup.- type layer. The diffusion regions are separated from each other by an insulation layer, but each in contact with a conductive film. Another conductive film is disposed on the insulation layer. The three conductive films are insulated from each other by the insulation layer and still another overlying insulation layer. Still other conductive films are formed on the upper insulation layer, and are coupled to the three conductive films. A wiring conductive film is also formed on the upper insulation layer. The wiring conductive film has a relatively small capacitance with the three conductive films. Due to the device structure, influence of the wiring conductive film over the surface of the semiconductor device is blocked by the conductive films.

Abstract: On the p.sup.- substrate, the n.sup.- epitaxial layer is surrounded and isolated by the p well. In the surface of the n.sup.- epitaxial layer, there is provided the p floating region in the vicinity of the p well, on which the sense electrode is provided. The insulation film and the conductive film are formed on the n.sup.- epitaxial layer between the p well and the p floating region to overlap them. The conductive film and the p floating region serve as a composite field plate, which makes it hard that the surface electric field distribution is influenced by the state of electric charge in the surface and relieves the surface electric field by expanding the depletion layer, which extends from the pn junction between the n.sup.- epitaxial layer and the p well into the n.sup.- epitaxial layer in current blocking state, toward the center of the n.sup.- epitaxial layer.

Abstract: On the p.sup.- substrate, the n.sup.- epitaxial layer is surrounded and isolated by the p well. In the surface of the n.sup.- epitaxial layer, there is provided the p floating region in the vicinity of the p well, on which the sense electrode is provided. The insulation film and the conductive film are formed on the n.sup.- epitaxial layer between the p well and the p floating region to overlap them. The conductive film and the p floating region serve as a composite field plate, which makes it hard that the surface electric field distribution is influenced by the state of electric charge in the surface and relieves the surface electric field by expanding the depletion layer, which extends from the pn junction between the n.sup.- epitaxial layer and the p well into the n.sup.- epitaxial layer in current blocking state, toward the center of the n.sup.- epitaxial layer.

Abstract: On the p.sup.- substrate, the n.sup.- epitaxial layer is surrounded and isolated by the p well. In the surface of the n.sup.- epitaxial layer, there is provided the p floating region in the vicinity of the p well, on which the sense electrode is provided. The insulation film and the conductive film are formed on the n.sup.- epitaxial layer between the p well and the p floating region to overlap them. The conductive film and the p floating region serve as a composite field plate, which makes it hard that the surface electric field distribution is influenced by the state of electric charge in the surface and relieves the surface electric field by expanding the depletion layer, which extends from the pn junction between the n.sup.31 epitaxial layer and the p well into the n.sup.- epitaxial layer in current blocking state, toward the center of the n.sup.- epitaxial layer.

Abstract: First and second semiconductor elements are formed in first and second semiconductor element forming regions which have the same thickness, include first and second semiconductor layers and are separated with dielectric isolation from each other. The thickness of the first semiconductor layer is made different between the first and second semiconductor element forming regions, so that the thickness of the second semiconductor layer becomes different between the first and second semiconductor element forming regions. Thus, the semiconductor device may have the semiconductor elements which have second semiconductor layers with different thicknesses in accordance with desired electrical characteristics for each of the semiconductor elements formed in the first and second semiconductor element forming regions, to complement a semiconductor device having the semiconductor elements each of which has independent optimum electrical characteristics.