Patents by Inventor Kazumasa Sonoda

Kazumasa Sonoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170078211
    Abstract: A transmission method executed by a transmission apparatus including a plurality of reception modules that receive packets and a plurality of transmission modules that receive the packets and transmit the packets to destinations of the packets, the transmission method includes extracting, by each of the plurality of reception modules, the amounts of data for respective priority levels of the received packets; transmitting, to one of the plurality of transmission modules, information regarding the extracted amounts of data for the respective priority levels; determining, by the one of the plurality of transmission modules, the amounts of discard data to be discarded for the plurality of respective reception modules, based on the extracted amounts of data for the respective priority levels and the amount of packet data that is able to be output; and notifying the plurality of reception modules of feedback information related to the determined amounts of discard data.
    Type: Application
    Filed: August 5, 2016
    Publication date: March 16, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Hideyo Fukunaga, MASAYOSHI MIHARA, Hideyuki KUDOU, Wataru Kanemori, Kazumasa Sonoda, Shinichi Fujiyoshi, YOSHINARI SUGIMOTO, Yoshikatsu KOHARA
  • Publication number: 20140101356
    Abstract: A transmission device includes a plurality of transmitting units that transmit data to an opposing device via different paths, a determining unit that compares a first speed of an operation clock for the opposing device with a second speed of an operation clock for the transmission device, and an inserting unit that inserts, when the first speed is same as the second speed, first difference absorbing data that has a predetermined data length into the data to be transmitted by the transmitting units, that inserts, when the first speed is higher, second difference absorbing data that has a data length smaller than the predetermined data length into the data, and that inserts, when the second speed is higher, third difference absorbing data that has a data length greater than the predetermined data length into the data.
    Type: Application
    Filed: December 11, 2013
    Publication date: April 10, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Kazumasa SONODA, Hideyuki KUDOU, Takahiro YAMAMOTO, Hiroo UCHIYAMA, Kozue FUKAMINATO
  • Publication number: 20080181231
    Abstract: A data processing device connected to another data processing device through an asynchronous network to receive/transmit data from/to the other data processing device. The data processing device monitors an accumulation amount of a reception buffer for receiving data transmitted from the other data processing device, controls a self reception data processing clock based upon the monitored accumulation amount, transmits to the other data processing device transmission clock control information controlling a transmission clock in the other data processing device based upon the monitored accumulation amount, and controlling a self transmission clock based upon the clock control information transmitted from the other data processing device.
    Type: Application
    Filed: January 4, 2008
    Publication date: July 31, 2008
    Applicant: Fujitsu Limited
    Inventors: Kazumasa SONODA, Satoru Mashima, Hideyuki Kudou, Akira Hashimoto, Takahiro Yamamoto
  • Publication number: 20050147106
    Abstract: A transmission system which can flexibly set/change VC mode and, in case of fault, can reset the VC mode to continue communication. A transmit-side VC mode setting unit sets a VC mode according to upper-level setting or path fault information. A transmit-side signal control unit controls signals in the VC mode. A path monitoring/setting unit generates a specific pattern. A first signal transmitting/receiving unit transmits the VC mode and the specific pattern to a remote device, and receives path fault information from the remote device. A second signal transmitting/receiving unit detects the VC mode and the specific pattern and transmits path fault information to the remote device. A receive-side VC mode setting unit sets the received VC mode. A receive-side signal control unit controls signals in the VC mode. Based on the specific pattern, a path monitoring/determination unit generates the path fault information indicative of a path connection determination result.
    Type: Application
    Filed: January 13, 2005
    Publication date: July 7, 2005
    Inventor: Kazumasa Sonoda
  • Patent number: 6789176
    Abstract: In a common buffering device with a simple arrangement, a write address can be efficiently released from a buffer memory upon receipt of a multi-address call. For an ATM cell which is to be transmitted to a specific line, a write address is set in a common buffer memory, and the ATM cell is written at the write address. The ATM cell is read from an address which corresponds to the write address, and is transmitted to the specific line. Then, the pertinent write address is released. In a write table are entered a plurality of multi-address lines across which an ATM cell written at a specific address in the common buffering device can be multicast. Each time the ATM cell is read from the specific address, a designation line for transmission of an ATM cell in a read control table is compared with the multi-address lines set in the write control table. When the lines match, the write address for the ATM cell, which is set in the write control table, is released.
    Type: Grant
    Filed: April 5, 1999
    Date of Patent: September 7, 2004
    Assignee: Fujitsu Limited
    Inventors: Shiro Uriu, Masanobu Furukoshi, Tetsuaki Wakabayashi, Kazumasa Sonoda
  • Publication number: 20020145995
    Abstract: In a common buffering device with a simple arrangement, a write address can be efficiently released from a buffer memory upon receipt of a multi-address call. For an ATM cell which is to be transmitted to a specific line, a write address is set in a common buffer memory, and the ATM cell is written at the write address. The ATM cell is read from an address which corresponds to the write address, and is transmitted to the specific line. Then, the pertinent write address is released. In a write table are entered a plurality of multi-address lines across which an ATM cell written at a specific address in the common buffering device can be multicast. Each time the ATM cell is read from the specific address, a designation line for transmission of an ATM cell in a read control table is compared with the multi-address lines set in the write control table. When the lines match, the write address for the ATM cell, which is set in the write control table, is released.
    Type: Application
    Filed: April 5, 1999
    Publication date: October 10, 2002
    Inventors: SHIRO URIU, MASANOBU FURUKOSHI, TETSUAKI WAKABAYASHI, KAZUMASA SONODA
  • Patent number: 6430157
    Abstract: A switching system in an ATM switching system accommodating an ABR is constructed of an individual units connected to a transmitting terminal or a receiving terminal to implement an efficient bandwidth authorization, and a plurality of intra-system relay devices having transmission allowed rate calculating units. In this switching system, there are separated a transfer of a management cell between the transmitting terminal or the receiving terminal and the individual unit and a transfer of the management cell between the plurality of intra-system relay devices.
    Type: Grant
    Filed: March 25, 1998
    Date of Patent: August 6, 2002
    Assignee: Fujitsu Limited
    Inventors: Shiro Uriu, Kazumasa Sonoda, Hiroshi Ishiwata
  • Publication number: 20020080722
    Abstract: A switching system in an ATM switching system accommodating an ABR is constructed of an individual units connected to a transmitting terminal or a receiving terminal to implement an efficient bandwidth authorization, and a plurality of intra-system relay devices having transmission allowed rate calculating units. In this switching system, there are separated a transfer of a management cell between the transmitting terminal or the receiving terminal and the individual unit and a transfer of the management cell between the plurality of intra-system relay devices.
    Type: Application
    Filed: March 25, 1998
    Publication date: June 27, 2002
    Inventors: SHIRO URIU, KAZUMASA SONODA, HIROSHI ISHIWATA
  • Patent number: 5958069
    Abstract: A system includes a host, first and second devices which operate as an acting device and a standby device, and a simplex unit controlled by the acting device. Each device is provided with a monitoring unit for monitoring the occurrence of failure, means for notifying the other device of a failure in its own device, and active/standby notification means. The active/standby notification means notifies the simplex unit that its own device is acting or standing by when the device becomes the acting device or standby device in response to a command from the host. Upon a failure in the other device when its own device is standing by, the active/standby notification means notifies the simplex unit that its own device is now an apparent acting device. Upon a failure in its own device when its own device is acting, the active/standby notification means notifies the simplex unit that its own device is now an apparent standby device.
    Type: Grant
    Filed: May 12, 1997
    Date of Patent: September 28, 1999
    Assignee: Fujitsu Limited
    Inventors: Hiroya Kawasaki, Masaki Kira, Shiro Uriu, Yukinaga Toyoda, Kazumasa Sonoda
  • Patent number: 5737338
    Abstract: A method of testing an ATM exchange having a redundant structure that includes an active system and a standby system includes the steps of transmitting a test cell from a testing device to both the active system and standby system, causing the test cell to pass through ATM switches in each of the active and standby systems, returning the test cell that has passed through the ATM switches of both systems to the testing device, and conducting a test of the ACT switches in the active and standby systems by comparing data contained in the transmitted test cell with data contained in a test cell received from the active system or standby system.
    Type: Grant
    Filed: August 2, 1995
    Date of Patent: April 7, 1998
    Assignee: Fujitsu Limited
    Inventors: Nobuhiko Eguchi, Hiroyuki Kudou, Kazumasa Sonoda, Naoki Aihara