Patents by Inventor Kazumasa Yamamoto

Kazumasa Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220371143
    Abstract: A workpiece installation method includes obtaining a reference image that shows a reference workpiece whose posture has been adjusted, setting workpiece reference lines on a boundary of a first image area occupied by the reference workpiece in the reference image, obtaining a measurement image that shows a workpiece, generating, using a processor, a measurement combined image in which workpiece reference lines are superimposed on the measurement image and which shows the workpiece reference lines pass through positions respectively identical to workpiece reference line positions, and adjusting a posture of the workpiece such that a boundary of a second image area occupied by the workpiece in the measurement combined image is shown to be substantially parallel to or substantially coincident with the workpiece reference lines.
    Type: Application
    Filed: August 5, 2022
    Publication date: November 24, 2022
    Applicant: Yamazaki Mazak Corporation
    Inventors: Kazuya HORIBE, Kazumasa MARUTA, Hiromasa YAMAMOTO, Hyunkoo PARK, Masatoshi ITOH, Ryuichi MIZUKAMI
  • Publication number: 20210165713
    Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.
    Type: Application
    Filed: February 12, 2021
    Publication date: June 3, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Marie TAKADA, Masamichi FUJIWARA, Kazumasa YAMAMOTO, Naoaki KOKUBUN, Tatsuro HITOMI, Hironori UCHIKAWA
  • Patent number: 10956264
    Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: March 23, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada, Masamichi Fujiwara, Kazumasa Yamamoto, Naoaki Kokubun, Tatsuro Hitomi, Hironori Uchikawa
  • Patent number: 10574272
    Abstract: A memory system includes a nonvolatile memory and a memory controller configured to perform reading of a concatenation code from the nonvolatile memory in response to an external command, the memory controller including a decoder circuit which decodes a reception word in the concatenation code. The decoder circuit includes a first external code decoder that performs decoding on an external code portion, an internal code in-error bit estimation unit that performs estimation of an in-error bit on a bit sequence from the first external code decoder, based on a rule for an internal code in the concatenation code, and outputs a set of in-error bits that is obtained by the estimation, and a second external code decoder that performs decoding which uses the set of in-error bits that is output from the internal code in-error bit estimation unit, on the bit sequence from the first external code decoder.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: February 25, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuta Kumano, Kazumasa Yamamoto, Hironori Uchikawa, Akira Yamaga
  • Publication number: 20190377636
    Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.
    Type: Application
    Filed: August 21, 2019
    Publication date: December 12, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Marie TAKADA, Masamichi FUJIWARA, Kazumasa YAMAMOTO, Naoaki KOKUBUN, Tatsuro HITOMI, Hironori UCHIKAWA
  • Patent number: 10430275
    Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: October 1, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada, Masamichi Fujiwara, Kazumasa Yamamoto, Naoaki Kokubun, Tatsuro Hitomi, Hironori Uchikawa
  • Publication number: 20190087264
    Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.
    Type: Application
    Filed: March 9, 2018
    Publication date: March 21, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada, Masamichi Fujiwara, Kazumasa Yamamoto, Naoaki Kokubun, Tatsuro Hitomi, Hironori Uchikawa
  • Publication number: 20190089384
    Abstract: A memory system includes a nonvolatile memory and a memory controller configured to perform reading of a concatenation code from the nonvolatile memory in response to an external command, the memory controller including a decoder circuit which decodes a reception word in the concatenation code. The decoder circuit includes a first external code decoder that performs decoding on an external code portion, an internal code in-error bit estimation unit that performs estimation of an in-error bit on a bit sequence from the first external code decoder, based on a rule for an internal code in the concatenation code, and outputs a set of in-error bits that is obtained by the estimation, and a second external code decoder that performs decoding which uses the set of in-error bits that is output from the internal code in-error bit estimation unit, on the bit sequence from the first external code decoder.
    Type: Application
    Filed: March 1, 2018
    Publication date: March 21, 2019
    Inventors: Yuta KUMANO, Kazumasa YAMAMOTO, Hironori UCHIKAWA, Akira YAMAGA
  • Patent number: 9166674
    Abstract: An object of the present invention is to provide a satellite communication device which receives instructions from a remote place and automatically carries out a predetermined process. The satellite communication device includes an acquiring section, a storing section, and a control section. The acquiring section acquires instruction information through an artificial satellite by line switching type communication. The storing section stores the instruction information and a registered process by established correspondence. The control section reads out a process corresponding to the instruction information acquired by the acquiring section based on storage contents of the storing section, and carries out the process that has been read out.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: October 20, 2015
    Assignee: FURUNO ELECTRIC COMPANY LIMITED
    Inventors: Satoshi Adachi, Katsuhiro Takahashi, Kazumasa Yamamoto
  • Publication number: 20140036761
    Abstract: An object of the present invention is to provide a satellite communication device which receives instructions from a remote place and automatically carries out a predetermined process. The satellite communication device includes an acquiring section, a storing section, and a control section. The acquiring section acquires instruction information through an artificial satellite by line switching type communication. The storing section stores the instruction information and a registered process by established correspondence. The control section reads out a process corresponding to the instruction information acquired by the acquiring section based on storage contents of the storing section, and carries out the process that has been read out.
    Type: Application
    Filed: July 30, 2013
    Publication date: February 6, 2014
    Applicant: Furuno Electric Company Limited
    Inventors: Satoshi ADACHI, Katsuhiro TAKAHASHI, Kazumasa YAMAMOTO
  • Patent number: 8612824
    Abstract: A semiconductor memory device includes: plural semiconductor memory chips to store information depending on an amount of accumulated charge; plural parameter storage units provided in correspondence with the semiconductor memory chips, each parameter to store therein a parameter that defines an electrical characteristic of a signal used for writing information into or reading information from a corresponding one of the semiconductor memory chips; an error correction encoding unit configured to generate a first correction code capable of correcting an error in the information stored in a number of semiconductor memory chips no greater than a predetermined number out of the semiconductor memory chips, from the information stored in the semiconductor memory chips; and a parameter processing unit configured to change the parameters respectively corresponding to the number of semiconductor memory chips no greater than the predetermined number, and write the parameters changed into the parameter storage units, resp
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: December 17, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumasa Yamamoto, Shinichi Kanno, Shigehiro Asano, Hiroyuki Nagashima
  • Publication number: 20120072795
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of semiconductor memory chips configured to store therein information depending on an amount of accumulated charge; a plurality of parameter storage units that are provided in correspondence with the semiconductor memory chips, each of the plurality of parameter storage units being configured to store therein a parameter that defines an electrical characteristic of a signal used for writing information into or reading information from a corresponding one of the semiconductor memory chips; an error correction encoding unit configured to generate a first correction code capable of correcting an error in the information stored in a number of semiconductor memory chips no greater than a predetermined number out of the semiconductor memory chips, from the information stored in the semiconductor memory chips; and a parameter processing unit configured to change the parameters respectively corresponding to the number of semiconductor mem
    Type: Application
    Filed: March 2, 2011
    Publication date: March 22, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazumasa YAMAMOTO, Shinichi KANNO, Shigehiro ASANO, Hiroyuki NAGASHIMA
  • Publication number: 20100111838
    Abstract: Brain-localizing polypeptides carrying a reactive group for linking to a molecule that does not have brain-localizing activity were successfully produced by introducing at least two lysine residues into cyclized polypeptides having a brain-localizing motif sequence. These polypeptides have improved metabolic stability compared to conventional brain-localizing polypeptides, and can efficiently translocate desired molecules into the brain.
    Type: Application
    Filed: February 27, 2008
    Publication date: May 6, 2010
    Applicants: Proteus Sciences Co., Ltd, National Institute of Radiological Sciences
    Inventors: Tomohiro Nakajo, Hirotaka Hara, Kazumasa Yamamoto, Hiromi Suzuki, Makoto Sawada, Tetsuya Suhara, Makoto Higuchi, Terushi Haradahira, Hin Ki
  • Publication number: 20090180947
    Abstract: To recycle fluoride by recovering calcium fluoride having a particle size and purity suitable for production of hydrogen fluoride, from a fluoride-containing effluent or a hydrofluoric acid-containing effluent. This method comprises reacting the fluoride-containing effluent or the hydrofluoric acid-containing effluent with an aqueous calcium chloride solution, under an acidic condition with hydrochloric acid where calcium fluoride has a comparatively high solubility. Calcium fluoride having a high purity and a large particle size can be deposited. The hydrochloric acid residues from the reaction or formed through the reaction is reacted with an inexpensive calcium compound such as calcium hydroxide, calcium oxide and calcium carbonate to produce an aqueous calcium chloride solution, and the aqueous calcium chloride solution is reused for the treatment of the hydrofluoric acid-containing effluent.
    Type: Application
    Filed: August 17, 2004
    Publication date: July 16, 2009
    Applicant: Morta Chemical Industrial Co., Ltd.
    Inventors: Kunitaka Momota, Kazumasa Yamamoto, Youichi Inoue, Shuuichi Watanabe
  • Patent number: 7366669
    Abstract: To provide an acoustic model which can absorb the fluctuation of a phonemic environment in an interval longer than a syllable, with the number of parameters of the acoustic model suppressed to be small, a phoneme-connected syllable HMM/syllable-connected HMM set is generated in such a way that a phoneme-connected syllable HMM set corresponding to individual syllables is generated by combining phoneme HMMs. A preliminary experiment is conducted using the phoneme-connected syllable HMM set and training speech data. Any misrecognized syllable and the preceding syllable of the misrecognized syllable are checked using results of a preliminary experiment syllable label data. The combination between a correct answer syllable for the misrecognized syllable and the preceding syllable of the misrecognized syllable is extracted as a syllable connection. A syllable-connected HMM corresponding to this syllable connection is added into the phoneme-connected syllable HMM set.
    Type: Grant
    Filed: March 8, 2004
    Date of Patent: April 29, 2008
    Assignee: Seiko Epson Corporation
    Inventors: Masanobu Nishitani, Yasunaga Miyazawa, Hiroshi Matsumoto, Kazumasa Yamamoto
  • Publication number: 20060089178
    Abstract: A cordless telephone set includes a charger base and a telephone apparatus. A concave retaining section of the charger base has an inclined surface and an open section. A power feeding terminal for supplying power with a charging terminal of the telephone apparatus is provided on a lower part of the inclined surface of the concave retaining section. A positioning member for restraining the telephone apparatus is provided at the lower part of the concave retaining section. A first distance between a support point at which the positioning member supports the telephone apparatus and a center of gravity of the telephone apparatus is in a positional relationship greater by a plurality of times than a second distance between the support point and a contact point where the charging terminal of the telephone apparatus is brought into contact with the power feeding terminal.
    Type: Application
    Filed: October 13, 2005
    Publication date: April 27, 2006
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Tohru Sakata, Toshiya Sakai, Mitsuhiro Haraguchi, Kazumasa Yamamoto, Atsushi Yamashita
  • Publication number: 20050154589
    Abstract: Exemplary embodiments of the present invention enhance the recognition ability by optimizing state numbers of respective HMM's. Exemplary embodiments provide a description length computing unit to find description lengths of respective syllable HMM's for which the number of states forming syllable HMM's is set to plural kinds of state numbers from a given value to the maximum state number, using the Minimum Description Length criterion, for each of syllable HMM's set to their respective state numbers. An HMM selecting unit selects an HMM having the state number with which the description length found by the description length computing device is a minimum. An HMM re-training unit re-trains the syllable HMM selected by the syllable HMM selecting unit with the use of training speech data.
    Type: Application
    Filed: November 18, 2004
    Publication date: July 14, 2005
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Masanobu Nishitani, Yasunaga Miyazawa, Hiroshi Matsumoto, Kazumasa Yamamoto
  • Publication number: 20050131694
    Abstract: Exemplary embodiments of the invention enhance the recognition ability by optimizing the distribution numbers for respective states that constitute an HMM (for example, a syllable HMM).
    Type: Application
    Filed: November 29, 2004
    Publication date: June 16, 2005
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Masanobu Nishitani, Yasunaga Miyazawa, Hiroshi Matsumoto, Kazumasa Yamamoto
  • Publication number: 20040236577
    Abstract: To provide an acoustic model which can absorb the fluctuation of a phonemic environment in an interval longer than a syllable, with the number of parameters of the acoustic model suppressed to be small, a phoneme-connected syllable HMM/syllable-connected HMM set is generated in such a way that a phoneme-connected syllable HMM set corresponding to individual syllables is generated by combining phoneme HMMs. A preliminary experiment is conducted using the phoneme-connected syllable HMM set and training speech data. Any misrecognized syllable and the preceding syllable of the misrecognized syllable are checked using results of a preliminary experiment syllable label data. The combination between a correct answer syllable for the misrecognized syllable and the preceding syllable of the misrecognized syllable is extracted as a syllable connection. A syllable-connected HMM corresponding to this syllable connection is added into the phoneme-connected syllable HMM set.
    Type: Application
    Filed: March 8, 2004
    Publication date: November 25, 2004
    Applicant: Seiko Epson Corporation
    Inventors: Masanobu Nishitani, Yasunaga Miyazawa, Hiroshi Matsumoto, Kazumasa Yamamoto
  • Publication number: 20040111263
    Abstract: The invention provides an acoustic model creating method that can reduce the number of parameters and optimize the Gaussian distribution number for respective states constituting an HMM in order to create an HMM having high recognition ability. HMM sets in which the Gaussian distribution numbers of the respective states constituting the respective syllable HMMs are set from one to the maximum distribution number (the distribution number of which is 64) is trained using training speech data, and the respective states of the respective HMMs are viterbi-aligned with the training speech data corresponding to the HMMs using a syllable HMM set to the maximum distribution number among the trained syllable HMM sets. Then, a description length computing unit computes a description length for the respective states of the respective HMMs using the alignment data, and a state selecting unit selects a state having the distribution number the description length of which is minimum.
    Type: Application
    Filed: September 17, 2003
    Publication date: June 10, 2004
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Masanobu Nishitani, Yasunaga Miyazawa, Hiroshi Matsumoto, Kazumasa Yamamoto