Patents by Inventor Kazumasa Yamamoto
Kazumasa Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11933638Abstract: A method for detecting a phase on a gear includes obtaining a first determination result indicating whether the gear has been detected at a first detection position. A second determination result indicating whether the gear has been detected at a second detection position is obtained. A third angle between the first and second angles is obtained. A third determination result indicating whether the gear has been detected at a third detection position is obtained. The first angle is replaced with the third angle when the third and first determination results are same, or the second angle is replaced with the third angle when the third and first determination results are different. The phase on the gear is detected based on an angle that is between the first angle and the second angle.Type: GrantFiled: August 6, 2020Date of Patent: March 19, 2024Assignee: YAMAZAKI MAZAK CORPORATIONInventors: Kazuya Horibe, Kazumasa Maruta, Hiromasa Yamamoto, Yuki Yamamoto
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Patent number: 11892907Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.Type: GrantFiled: November 10, 2022Date of Patent: February 6, 2024Assignee: Kioxia CorporationInventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada, Masamichi Fujiwara, Kazumasa Yamamoto, Naoaki Kokubun, Tatsuro Hitomi, Hironori Uchikawa
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Publication number: 20230065159Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.Type: ApplicationFiled: November 10, 2022Publication date: March 2, 2023Applicant: Kioxia CorporationInventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Marie TAKADA, Masamichi FUJIWARA, Kazumasa YAMAMOTO, Naoaki KOKUBUN, Tatsuro HITOMI, Hironori UCHIKAWA
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Patent number: 11537465Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.Type: GrantFiled: February 12, 2021Date of Patent: December 27, 2022Assignee: KIOXIA CORPORATIONInventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada, Masamichi Fujiwara, Kazumasa Yamamoto, Naoaki Kokubun, Tatsuro Hitomi, Hironori Uchikawa
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Publication number: 20210165713Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.Type: ApplicationFiled: February 12, 2021Publication date: June 3, 2021Applicant: Toshiba Memory CorporationInventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Marie TAKADA, Masamichi FUJIWARA, Kazumasa YAMAMOTO, Naoaki KOKUBUN, Tatsuro HITOMI, Hironori UCHIKAWA
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Patent number: 10956264Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.Type: GrantFiled: August 21, 2019Date of Patent: March 23, 2021Assignee: Toshiba Memory CorporationInventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada, Masamichi Fujiwara, Kazumasa Yamamoto, Naoaki Kokubun, Tatsuro Hitomi, Hironori Uchikawa
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Patent number: 10574272Abstract: A memory system includes a nonvolatile memory and a memory controller configured to perform reading of a concatenation code from the nonvolatile memory in response to an external command, the memory controller including a decoder circuit which decodes a reception word in the concatenation code. The decoder circuit includes a first external code decoder that performs decoding on an external code portion, an internal code in-error bit estimation unit that performs estimation of an in-error bit on a bit sequence from the first external code decoder, based on a rule for an internal code in the concatenation code, and outputs a set of in-error bits that is obtained by the estimation, and a second external code decoder that performs decoding which uses the set of in-error bits that is output from the internal code in-error bit estimation unit, on the bit sequence from the first external code decoder.Type: GrantFiled: March 1, 2018Date of Patent: February 25, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yuta Kumano, Kazumasa Yamamoto, Hironori Uchikawa, Akira Yamaga
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Publication number: 20190377636Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.Type: ApplicationFiled: August 21, 2019Publication date: December 12, 2019Applicant: Toshiba Memory CorporationInventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Marie TAKADA, Masamichi FUJIWARA, Kazumasa YAMAMOTO, Naoaki KOKUBUN, Tatsuro HITOMI, Hironori UCHIKAWA
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Patent number: 10430275Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.Type: GrantFiled: March 9, 2018Date of Patent: October 1, 2019Assignee: Toshiba Memory CorporationInventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada, Masamichi Fujiwara, Kazumasa Yamamoto, Naoaki Kokubun, Tatsuro Hitomi, Hironori Uchikawa
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Publication number: 20190087264Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.Type: ApplicationFiled: March 9, 2018Publication date: March 21, 2019Applicant: Toshiba Memory CorporationInventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada, Masamichi Fujiwara, Kazumasa Yamamoto, Naoaki Kokubun, Tatsuro Hitomi, Hironori Uchikawa
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Publication number: 20190089384Abstract: A memory system includes a nonvolatile memory and a memory controller configured to perform reading of a concatenation code from the nonvolatile memory in response to an external command, the memory controller including a decoder circuit which decodes a reception word in the concatenation code. The decoder circuit includes a first external code decoder that performs decoding on an external code portion, an internal code in-error bit estimation unit that performs estimation of an in-error bit on a bit sequence from the first external code decoder, based on a rule for an internal code in the concatenation code, and outputs a set of in-error bits that is obtained by the estimation, and a second external code decoder that performs decoding which uses the set of in-error bits that is output from the internal code in-error bit estimation unit, on the bit sequence from the first external code decoder.Type: ApplicationFiled: March 1, 2018Publication date: March 21, 2019Inventors: Yuta KUMANO, Kazumasa YAMAMOTO, Hironori UCHIKAWA, Akira YAMAGA
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Patent number: 9166674Abstract: An object of the present invention is to provide a satellite communication device which receives instructions from a remote place and automatically carries out a predetermined process. The satellite communication device includes an acquiring section, a storing section, and a control section. The acquiring section acquires instruction information through an artificial satellite by line switching type communication. The storing section stores the instruction information and a registered process by established correspondence. The control section reads out a process corresponding to the instruction information acquired by the acquiring section based on storage contents of the storing section, and carries out the process that has been read out.Type: GrantFiled: July 30, 2013Date of Patent: October 20, 2015Assignee: FURUNO ELECTRIC COMPANY LIMITEDInventors: Satoshi Adachi, Katsuhiro Takahashi, Kazumasa Yamamoto
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Publication number: 20140036761Abstract: An object of the present invention is to provide a satellite communication device which receives instructions from a remote place and automatically carries out a predetermined process. The satellite communication device includes an acquiring section, a storing section, and a control section. The acquiring section acquires instruction information through an artificial satellite by line switching type communication. The storing section stores the instruction information and a registered process by established correspondence. The control section reads out a process corresponding to the instruction information acquired by the acquiring section based on storage contents of the storing section, and carries out the process that has been read out.Type: ApplicationFiled: July 30, 2013Publication date: February 6, 2014Applicant: Furuno Electric Company LimitedInventors: Satoshi ADACHI, Katsuhiro TAKAHASHI, Kazumasa YAMAMOTO
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Patent number: 8612824Abstract: A semiconductor memory device includes: plural semiconductor memory chips to store information depending on an amount of accumulated charge; plural parameter storage units provided in correspondence with the semiconductor memory chips, each parameter to store therein a parameter that defines an electrical characteristic of a signal used for writing information into or reading information from a corresponding one of the semiconductor memory chips; an error correction encoding unit configured to generate a first correction code capable of correcting an error in the information stored in a number of semiconductor memory chips no greater than a predetermined number out of the semiconductor memory chips, from the information stored in the semiconductor memory chips; and a parameter processing unit configured to change the parameters respectively corresponding to the number of semiconductor memory chips no greater than the predetermined number, and write the parameters changed into the parameter storage units, respType: GrantFiled: March 2, 2011Date of Patent: December 17, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Kazumasa Yamamoto, Shinichi Kanno, Shigehiro Asano, Hiroyuki Nagashima
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Publication number: 20120072795Abstract: According to one embodiment, a semiconductor memory device includes a plurality of semiconductor memory chips configured to store therein information depending on an amount of accumulated charge; a plurality of parameter storage units that are provided in correspondence with the semiconductor memory chips, each of the plurality of parameter storage units being configured to store therein a parameter that defines an electrical characteristic of a signal used for writing information into or reading information from a corresponding one of the semiconductor memory chips; an error correction encoding unit configured to generate a first correction code capable of correcting an error in the information stored in a number of semiconductor memory chips no greater than a predetermined number out of the semiconductor memory chips, from the information stored in the semiconductor memory chips; and a parameter processing unit configured to change the parameters respectively corresponding to the number of semiconductor memType: ApplicationFiled: March 2, 2011Publication date: March 22, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazumasa YAMAMOTO, Shinichi KANNO, Shigehiro ASANO, Hiroyuki NAGASHIMA
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Publication number: 20100111838Abstract: Brain-localizing polypeptides carrying a reactive group for linking to a molecule that does not have brain-localizing activity were successfully produced by introducing at least two lysine residues into cyclized polypeptides having a brain-localizing motif sequence. These polypeptides have improved metabolic stability compared to conventional brain-localizing polypeptides, and can efficiently translocate desired molecules into the brain.Type: ApplicationFiled: February 27, 2008Publication date: May 6, 2010Applicants: Proteus Sciences Co., Ltd, National Institute of Radiological SciencesInventors: Tomohiro Nakajo, Hirotaka Hara, Kazumasa Yamamoto, Hiromi Suzuki, Makoto Sawada, Tetsuya Suhara, Makoto Higuchi, Terushi Haradahira, Hin Ki
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Publication number: 20090180947Abstract: To recycle fluoride by recovering calcium fluoride having a particle size and purity suitable for production of hydrogen fluoride, from a fluoride-containing effluent or a hydrofluoric acid-containing effluent. This method comprises reacting the fluoride-containing effluent or the hydrofluoric acid-containing effluent with an aqueous calcium chloride solution, under an acidic condition with hydrochloric acid where calcium fluoride has a comparatively high solubility. Calcium fluoride having a high purity and a large particle size can be deposited. The hydrochloric acid residues from the reaction or formed through the reaction is reacted with an inexpensive calcium compound such as calcium hydroxide, calcium oxide and calcium carbonate to produce an aqueous calcium chloride solution, and the aqueous calcium chloride solution is reused for the treatment of the hydrofluoric acid-containing effluent.Type: ApplicationFiled: August 17, 2004Publication date: July 16, 2009Applicant: Morta Chemical Industrial Co., Ltd.Inventors: Kunitaka Momota, Kazumasa Yamamoto, Youichi Inoue, Shuuichi Watanabe
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Patent number: 7366669Abstract: To provide an acoustic model which can absorb the fluctuation of a phonemic environment in an interval longer than a syllable, with the number of parameters of the acoustic model suppressed to be small, a phoneme-connected syllable HMM/syllable-connected HMM set is generated in such a way that a phoneme-connected syllable HMM set corresponding to individual syllables is generated by combining phoneme HMMs. A preliminary experiment is conducted using the phoneme-connected syllable HMM set and training speech data. Any misrecognized syllable and the preceding syllable of the misrecognized syllable are checked using results of a preliminary experiment syllable label data. The combination between a correct answer syllable for the misrecognized syllable and the preceding syllable of the misrecognized syllable is extracted as a syllable connection. A syllable-connected HMM corresponding to this syllable connection is added into the phoneme-connected syllable HMM set.Type: GrantFiled: March 8, 2004Date of Patent: April 29, 2008Assignee: Seiko Epson CorporationInventors: Masanobu Nishitani, Yasunaga Miyazawa, Hiroshi Matsumoto, Kazumasa Yamamoto
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Publication number: 20060089178Abstract: A cordless telephone set includes a charger base and a telephone apparatus. A concave retaining section of the charger base has an inclined surface and an open section. A power feeding terminal for supplying power with a charging terminal of the telephone apparatus is provided on a lower part of the inclined surface of the concave retaining section. A positioning member for restraining the telephone apparatus is provided at the lower part of the concave retaining section. A first distance between a support point at which the positioning member supports the telephone apparatus and a center of gravity of the telephone apparatus is in a positional relationship greater by a plurality of times than a second distance between the support point and a contact point where the charging terminal of the telephone apparatus is brought into contact with the power feeding terminal.Type: ApplicationFiled: October 13, 2005Publication date: April 27, 2006Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Tohru Sakata, Toshiya Sakai, Mitsuhiro Haraguchi, Kazumasa Yamamoto, Atsushi Yamashita
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Publication number: 20050154589Abstract: Exemplary embodiments of the present invention enhance the recognition ability by optimizing state numbers of respective HMM's. Exemplary embodiments provide a description length computing unit to find description lengths of respective syllable HMM's for which the number of states forming syllable HMM's is set to plural kinds of state numbers from a given value to the maximum state number, using the Minimum Description Length criterion, for each of syllable HMM's set to their respective state numbers. An HMM selecting unit selects an HMM having the state number with which the description length found by the description length computing device is a minimum. An HMM re-training unit re-trains the syllable HMM selected by the syllable HMM selecting unit with the use of training speech data.Type: ApplicationFiled: November 18, 2004Publication date: July 14, 2005Applicant: SEIKO EPSON CORPORATIONInventors: Masanobu Nishitani, Yasunaga Miyazawa, Hiroshi Matsumoto, Kazumasa Yamamoto