Patents by Inventor Kazumi Hara

Kazumi Hara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240079103
    Abstract: An information processing device (40) according to one embodiment of the present disclosure includes: an analysis unit (41) being a first data generation unit that generates objective score data, which indicates objective scores in time series, based on a plurality of pieces of objective data regarding a patient; a processing unit (42) being a second data generation unit that generates subjective score data, which indicates subjective scores in time series, based on a plurality of pieces of subjective data obtained from the patient; and a generation unit (44) being an image generation unit that generates a score image indicating the objective score data and the subjective score data.
    Type: Application
    Filed: December 23, 2021
    Publication date: March 7, 2024
    Inventors: RITSUKO KANO, EIJIRO MORI, SHINSUKE NOGUCHI, KAZUMI HIRANO, TAKAFUMI YANAGIMOTO, KOJI SATO, HIROSHI HARA
  • Patent number: 11693545
    Abstract: A display control device includes: a display region setting unit for changing a position of a boundary line of display regions provided on a screen to dynamically change a size of the display regions, in accordance with an event; a display control unit provides arrangement regions for arranging display objects in the display regions, and change a relative positional relationship of the arrangement regions on the same display region of the display regions, in accordance with change in size of the one or plurality of display regions; and a priority setting unit for setting relative priority regarding the arrangement regions, wherein where the relative positional relationship between the arrangement regions is changed, which causes the arrangement regions to be within a predetermined distance, the display control unit controls display of the display objects arranged on a same arrangement region based on the priority set regarding the arrangement regions.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: July 4, 2023
    Assignee: Faurecia Clarion Electronics Co., Ltd.
    Inventors: Jitsu Ezaki, Kazumi Hara
  • Publication number: 20230017397
    Abstract: A display control device includes: a display region setting unit for changing a position of a boundary line of display regions provided on a screen to dynamically change a size of the display regions, in accordance with an event; a display control unit provides arrangement regions for arranging display objects in the display regions, and change a relative positional relationship of the arrangement regions on the same display region of the display regions, in accordance with change in size of the one or plurality of display regions; and a priority setting unit for setting relative priority regarding the arrangement regions, wherein where the relative positional relationship between the arrangement regions is changed, which causes the arrangement regions to be within a predetermined distance, the display control unit controls display of the display objects arranged on a same arrangement region based on the priority set regarding the arrangement regions.
    Type: Application
    Filed: December 15, 2020
    Publication date: January 19, 2023
    Applicant: Faurecia Clarion Electronics Co., Ltd.
    Inventors: Jitsu EZAKI, Kazumi HARA
  • Patent number: 9257404
    Abstract: A semiconductor device includes a semiconductor substrate and a through electrode provided in a through hole formed in the semiconductor substrate. The through electrode partially protrudes from a back surface of the semiconductor substrate, which is opposite to an active surface thereof. The through electrode includes a resin core and a conductive film covering at least a part of the resin core.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: February 9, 2016
    Assignee: Seiko Epson Corporation
    Inventors: Tsuyoshi Yoda, Kazumi Hara
  • Publication number: 20140306342
    Abstract: A semiconductor device includes a semiconductor substrate and a through electrode provided in a through hole formed in the semiconductor substrate. The through electrode partially protrudes from a back surface of the semiconductor substrate, which is opposite to an active surface thereof. The through electrode includes a resin core and a conductive film covering at least a part of the resin core.
    Type: Application
    Filed: June 26, 2014
    Publication date: October 16, 2014
    Inventors: Tsuyoshi YODA, Kazumi HARA
  • Patent number: 8804316
    Abstract: A package includes a base member and a lid member joined to the base member while forming, between the lid and base members, an internal space which stores an electronic component. A joined section of the base and lid members includes a first welded section formed by joining the base and lid members along an x axis direction using seam welding and a second welded section formed by joining the base and lid members along a y axis direction using the seam welding. In plan view, the first and second welded sections do not overlap each other. An area where an area formed by extending the first welded section in the x axis direction and an area formed by extending the second welded section in the y axis direction overlap each other is located on the outer side with respect to the contour of the lid member.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: August 12, 2014
    Assignee: Seiko Epson Corporation
    Inventors: Manabu Shiraki, Tadanori Yamada, Kazumi Hara, Kazuhiko Shimodaira
  • Patent number: 8796823
    Abstract: A semiconductor device includes a semiconductor substrate and a through electrode provided in a through hole formed in the semiconductor substrate. The through electrode partially protrudes from a back surface of the semiconductor substrate, which is opposite to an active surface thereof. The through electrode includes a resin core and a conductive film covering at least a part of the resin core.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: August 5, 2014
    Assignee: Seiko Epson Corporation
    Inventors: Tsuyoshi Yoda, Kazumi Hara
  • Publication number: 20130010412
    Abstract: A package includes a base member and a lid member joined to the base member while forming, between the lid and base members, an internal space which stores an electronic component. A joined section of the base and lid members includes a first welded section formed by joining the base and lid members along an x axis direction using seam welding and a second welded section formed by joining the base and lid members along a y axis direction using the seam welding. In plan view, the first and second welded sections do not overlap each other. An area where an area formed by extending the first welded section in the x axis direction and an area formed by extending the second welded section in the y axis direction overlap each other is located on the outer side with respect to the contour of the lid member.
    Type: Application
    Filed: July 2, 2012
    Publication date: January 10, 2013
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Manabu SHIRAKI, Tadanori YAMADA, Kazumi HARA, Kazuhiko SHIMODAIRA
  • Patent number: 8330256
    Abstract: A semiconductor device includes a semiconductor substrate and a through electrode provided in a through hole formed in the semiconductor substrate. The through electrode partially protrudes from a back surface of the semiconductor substrate, which is opposite to an active surface thereof. The through electrode includes a resin core and a conductive film covering at least a part of the resin core.
    Type: Grant
    Filed: November 17, 2009
    Date of Patent: December 11, 2012
    Assignee: Seiko Epson Corporation
    Inventors: Tsuyoshi Yoda, Kazumi Hara
  • Publication number: 20100123256
    Abstract: A semiconductor device includes a semiconductor substrate and a through electrode provided in a through hole formed in the semiconductor substrate. The through electrode partially protrudes from a back surface of the semiconductor substrate, which is opposite to an active surface thereof. The through electrode includes a resin core and a conductive film covering at least a part of the resin core.
    Type: Application
    Filed: November 17, 2009
    Publication date: May 20, 2010
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Tsuyoshi YODA, Kazumi HARA
  • Patent number: 7410908
    Abstract: A manufacturing method for a semiconductor device, includes: preparing a semiconductor wafer having an active surface, a side surface, a rear surface on the side opposite the active surface, and a plurality of semiconductor elements formed on the active surface; forming the side surface of the semiconductor wafer so that an angle defined by at least a portion of the side surface of the semiconductor wafer and the rear surface of the semiconductor wafer becomes an acute angle; and performing a spin etching in which etching liquid is dripped onto the rear surface of the semiconductor wafer while blowing air toward the active surface of the semiconductor wafer and toward the side surface of the semiconductor wafer and while rotating the semiconductor wafer.
    Type: Grant
    Filed: June 1, 2006
    Date of Patent: August 12, 2008
    Assignee: Seiko Epson Corporation
    Inventor: Kazumi Hara
  • Patent number: 7402503
    Abstract: A dicing sheet which supports electronic-component aggregation with adhesive in the case of separating the electronic-component aggregation in which a plurality of electronic components are integrated, has a substrate and an adhesion layer which is formed at one surface side of the substrate, in which a concave portion is formed on a surface of the adhesion layer, and the concave portion is formed so that a convex shape member projected from an adhesion surface of the electronic-component aggregation which is adhered to the dicing sheet is inserted.
    Type: Grant
    Filed: June 22, 2005
    Date of Patent: July 22, 2008
    Assignee: Seiko Epson Corporation
    Inventor: Kazumi Hara
  • Patent number: 7387945
    Abstract: A semiconductor chip is provided that is highly packageable and particularly well suited for mounting on a circuit board having a curved surface. The semiconductor chip comprises a warpage control film that controls the warpage of a substrate.
    Type: Grant
    Filed: April 27, 2005
    Date of Patent: June 17, 2008
    Assignee: Seiko Epson Corporation
    Inventor: Kazumi Hara
  • Patent number: 7358602
    Abstract: A semiconductor chip includes: a semiconductor substrate; a penetrating electrode which is formed through the semiconductor substrate from a first surface to a second surface of the semiconductor substrate and has a projection which projects from the second surface; an insulating layer formed over an entire surface of the second surface. The insulating layer includes a first insulating section formed in a region around the projection and a second insulating section other than the first insulating section. The second insulating section is formed to be thinner than a thickest area of the first insulating section.
    Type: Grant
    Filed: January 14, 2004
    Date of Patent: April 15, 2008
    Assignee: Seiko Epson Corporation
    Inventor: Kazumi Hara
  • Patent number: 7255428
    Abstract: There is provided a droplet ejection head that is small in size, provides high productivity, and is extremely reliable. The droplet ejection head of the present invention includes pressure generating chambers that are connected to nozzle apertures, an elastic membrane (i.e., a diaphragm) that constitutes a portion of the pressure generating chambers, piezoelectric elements that are placed on a surface of the elastic membrane on the opposite side from the pressure generating chambers, and cause pressure changes to be generated inside the pressure generating chambers, and drive IC (i.e., drive elements) that drive the piezoelectric elements. In this droplet ejection head, the drive IC are flip-chip bonded to terminals that are provided on the piezoelectric elements.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: August 14, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Kazumi Hara
  • Publication number: 20060292887
    Abstract: A manufacturing method for a semiconductor device, includes: preparing a semiconductor wafer having an active surface, a side surface, a rear surface on the side opposite the active surface, and a plurality of semiconductor elements formed on the active surface; forming the side surface of the semiconductor wafer so that an angle defined by at least a portion of the side surface of the semiconductor wafer and the rear surface of the semiconductor wafer becomes an acute angle; and performing a spin etching in which etching liquid is dripped onto the rear surface of the semiconductor wafer while blowing air toward the active surface of the semiconductor wafer and toward the side surface of the semiconductor wafer and while rotating the semiconductor wafer.
    Type: Application
    Filed: June 1, 2006
    Publication date: December 28, 2006
    Inventor: Kazumi Hara
  • Publication number: 20060082616
    Abstract: There is provided a droplet ejection head that is small in size, provides high productivity, and is extremely reliable. The droplet ejection head of the present invention includes pressure generating chambers that are connected to nozzle apertures, an elastic membrane (i.e., a diaphragm) that constitutes a portion of the pressure generating chambers, piezoelectric elements that are placed on a surface of the elastic membrane on the opposite side from the pressure generating chambers, and cause pressure changes to be generated inside the pressure generating chambers, and drive IC (i.e., drive elements) that drive the piezoelectric elements. In this droplet ejection head, the drive IC are flip-chip bonded to terminals that are provided on the piezoelectric elements.
    Type: Application
    Filed: September 16, 2005
    Publication date: April 20, 2006
    Inventor: Kazumi Hara
  • Publication number: 20060009009
    Abstract: A dicing sheet which supports electronic-component aggregation with adhesive in the case of separating the electronic-component aggregation in which a plurality of electronic components are integrated, has a substrate and an adhesion layer which is formed at one surface side of the substrate, in which a concave portion is formed on a surface of the adhesion layer, and the concave portion is formed so that a convex shape member projected from an adhesion surface of the electronic-component aggregation which is adhered to the dicing sheet is inserted.
    Type: Application
    Filed: June 22, 2005
    Publication date: January 12, 2006
    Inventor: Kazumi Hara
  • Publication number: 20050253235
    Abstract: A semiconductor chip is provided that is highly packageable and particularly well suited for mounting on a circuit board having a curved surface. The semiconductor chip comprises a warpage control film that controls the warpage of a substrate.
    Type: Application
    Filed: April 27, 2005
    Publication date: November 17, 2005
    Inventor: Kazumi Hara
  • Publication number: 20040245623
    Abstract: A semiconductor device includes a semiconductor substrate with a through hole formed therein, a first insulating film formed inside the through hole, and an electrode formed on an inner side of the first insulating film inside the through hole. The first insulating film at the rear surface side of the semiconductor substrate protrudes beyond the rear surface, and the electrode protrudes on both the active surface side and the rear surface side of the semiconductor substrate. An outer diameter of a protruding portion on the active surface side is larger than an outer diameter of the first insulating film inside the through hole, and a protruding portion on the rear surface side protrudes further beyond the first insulating film to have a side surface thereof exposed. The semiconductor device has improved connectivity and connection strength and, in particular, has excellent resistance to shearing force when used in three-dimensional packaging technology.
    Type: Application
    Filed: March 5, 2004
    Publication date: December 9, 2004
    Inventors: Kazumi Hara, Yoshihiko Yokoyama, Ikuya Miyazawa, Koji Yamaguchi