Abstract: A semiconductor integrated circuit is provided whose area overhead due to provision of test points is reduced together with the test time period. In a semiconductor integrated circuit having a plurality of observation points in a tested circuit, the plurality of observation points are divided into a preset number of groups. The semiconductor integrated circuit contains at least one compressing circuit to reduce the number of bits of a multi-bit signal and to output the result (a signal of less bits) to an observable element such as an external output element or a flip-flop with a scan function. The semiconductor integrated circuit also has at least two scan chains each of which is made up with a plurality of flip-flop circuits working as shift registers. Further, the two scan chains are interconnected with a single input terminal.

Abstract: A semiconductor integrated circuit test method which reduces the required data volume for testing and efficiently detects faults in a circuit to be tested, the method comprising means 110 to generate identical pattern sequences repeatedly and means 120 to control flipped bits in pattern sequences, in order to generate neighborhood pattern sequences and use the neighborhood patterns to test the circuit under test 130. The neighborhood patterns include, in whole or in part, such pattern sequences as ones without flipped bits, ones with all or some flipped bits in one pattern and ones with all or some flipped bits in consecutive patterns or patterns at regular intervals, the interval being equivalent to a given number of patterns.

Abstract: The present invention relates to an LSI which performs a self test using its built-in test function according to a test program stored in an on-chip memory. An object of the present invention is to efficiently perform the self test in the case where branching to an address out of the address space of the on-chip memory occurs. A program counter 101 stores addresses of a memory 117 and an external memory. A test program counter 108 stores an address of the memory 117. In a test mode, a program counter switching section 109 performs control so that when an address of the memory 117 is detected in the program counter 101, the address value of the program counter 101 is selected, whereas when an address of the external memory is detected in the program counter 101, the address value of the test program counter 108 is selected. A signature compression circuit 110 signature-compresses and holds the output value of the program counter 101.

Abstract: A semiconductor integrated circuit is provided whose area overhead due to provision of test points is reduced together with the test time period. In a semiconductor integrated circuit having a plurality of observation points in a tested circuit, the plurality of observation points are divided into a preset number of groups. The semiconductor integrated circuit contains at least one compressing circuit to reduce the number of bits of a multi-bit signal and to output the result (a signal of less bits) to an observable element such as an external output element or a flip-flop with a scan function. The semiconductor integrated circuit also has at least two scan chains each of which is made up with a plurality of flip-flop circuits working as shift registers. Further, the two scan chains are interconnected with a single input terminal.

Abstract: An execution time of a built-in test utilizing a decoder can be shortened by setting in parallel the codes of test pattern generator during execution of a self-test in order to eliminate an event that a test execution time increases due to increase of the time required for setting the test codes when the number of test codes increases. Namely a semiconductor integrated circuit with a built-in test (BIT) function is provided with a test code backup register for storing the codes of a test pattern generator, a test clock generator and a BIT controller to realize a function to set the codes required for execution of the next self-test in parallel to execution of the self-test and a function to immediately shift to the next self-test upon completion of the first self-test execution. A tester periodically observes a self-test end signal BEND during execution of a self-test and immediately applies the next code to the semiconductor integrated circuit when it observes a signal indicating the end of the self-test.

Abstract: A method for designing a semiconductor integrated circuit while minimizing any increase in the area of its logic circuit under test. Circuit data about the semiconductor integrated circuit are received, and transition signal occurrence probabilities of all scanning function-equipped storage elements involved are computed by use of the circuit data. In keeping with the transition signal occurrence probabilities thus computed and based on predetermined parameters, the method permits selection of scanning function-equipped storage elements that may be replaced by delay test-ready scanning function-equipped storage elements.

Abstract: The present invention relates to an LSI which performs a self test using its built-in test function according to a test program stored in an on-chip memory. An object of the present invention is to efficiently perform the self test in the case where branching to an address out of the address space of the on-chip memory occurs.

Abstract: A semiconductor integrated circuit test method which reduces the required data volume for testing and efficiently detects faults in a circuit to be tested, the method comprising means 110 to generate identical pattern sequences repeatedly and means 120 to control flipped bits in pattern sequences, in order to generate neighborhood pattern sequences and use the neighborhood patterns to test the circuit under test 130. The neighborhood patterns include, in whole or in part, such pattern sequences as ones without flipped bits, ones with all or some flipped bits in one pattern and ones with all or some flipped bits in consecutive patterns or patterns at regular intervals, the interval being equivalent to a given number of patterns.

Abstract: An apparatus for providing test data used for detection of defects which occur in manufacturing functional blocks of a processor LSI is provided with a test pattern producing part for detecting a fault of the functional block at a block edge of the functional block, based on logic data of the functional block, with regard to one operation of the processor LSI which operates the functional block for the test data to be produced, the test pattern at the block edge of the functional block being such as to satisfy the conditions of an input signal to the block edge of the functional block when an instruction on the one operation is executed, and the conditions of an output signal from the block edge of the functional block being observable from the outside of the processor LSI when the instruction is executed.

Abstract: A test point analyzing apparatus determines a distinction between capability and incapability of insertion of a test point and a circuit modifying way when a test point is capable of being inserted for each of the test point types to each of the signal lines in a semiconductor integrated circuit by using circuit information, a test point insertion library, and test point insertion. Then, test point indexes to test point candidates capable of being inserted are calculated, and test point candidates having a large testability are selected based on the indexes, and the selected test point candidates are registered in test point information. Such processing is repeated until a predetermined condition of completing the test point analysis process is realized.

Abstract: An apparatus for producing test data used for detection of defects which occur in manufacturing functional blocks of a processor LSI is provided with a test pattern producing part for detecting a fault of the functional block at a block edge of the functional block, based on logic data of the functional block, with regard to one operation of the processor LSI which operates the functional block for the test data to be produced, the test pattern at the block edge of the functional block being such as to satisfy the conditions of an input signal to the block edge of the functional block when an instruction on the one operation is executed, and the conditions of an output signal from the block edge of the functional block being observable from the outside of the processor LSI when the instruction is executed.

Abstract: The first and second flip-flop circuits are connected in series included within a combinational logic for carrying out a delay test. The first and second flip-flop circuits are provided with control pins, system clock pins, scan clock pins, system data pins and scan data pins, respectively. A delay time propagated from the first flip-flop circuit to the second flip-flop circuit through the path of the combinational logic to be tested is measured by detecting an input time to the first flip-flop circuit by the system clock signal to the first flip-flop circuit in response to an input signal to the control pins and a time stored in the second flip-flop circuit corresponding to output system data from the first flip-flop circuit. By measuring the delay time, whether the combinational logic is normal or abnormal is detected.

Abstract: A memory incorporating logic Large Scale Integration (LSI) and a method for testing the same LSI includes signal path switching circuit portions which are disposed in the paths of a memory portion and a logic circuit portion. A test signal input and an output signal can be observed at an input and output terminal portion so as to be able to effect a dynamic function test of the memory portion. Further there is disposed a logic circuit test signal memory circuit portion, which switches over the signal path switching circuit portions to the logic circuit portion so as to be able to effect a test of the logic circuit portion, independently of the state of the memory portion.

Abstract: Disclosed is a method of level sensitive testing of a logic array system and an LSI chip having testing means incorporated therein. The present invention is especially suitable for testing a RAM and the function of a logic unit which is a functional peripheral of the RAM. The LSI chip comprises means for selecting a specific address of the RAM, means for writing a signal at the specific address of the RAM and reading out the data from the specific address of the RAM, and means for selecting the operation of the chip between a usual operation mode and a scan-in/scan-out diagnostic mode for testing the RAM or functional peripheral of the RAM. Testing can be easily conducted by addition of a small number of logic elements. The larger the number of address signal lines and the number of data signal lines of the RAM, the more effective the testing method becomes.

Abstract: A method of diagnosing an integrated circuit device having a plurality of combinational circuits, at least one input memory circuit connected to an input side of the combinational circuits, and an output memory circuit connected to an output side of the combinational circuits is disclosed. An input diagnostic signal is selectively applied to at least one input memory circuit connected to a given one of the combinational circuits, to read out a diagnostic signal stored in an output memory circuit connected to the given combinational circuit. Further, an integrated circuit device is disclosed which is suited to be diagnosed in the above method.