Abstract: Channels have NAND flash memories. Data processing units perform data processing on the NAND flash memories by using the channels according to a data processing command from a CPU. A configuration register stores therein a configuration of groups into which the channels are classified based on processing performances of the respective channels, and stores therein assignments of the data processing units that perform data processing by using the channels contained in each of the groups. The group identifying unit selects a group for performing data processing from among the groups stored in the configuration register based on the data processing command from the CPU, and causes the data processing unit assigned to the selected group to perform the data processing.

Abstract: An address translation table stores therein an association relation between a logical address and a physical address, change information indicating a change in the association relation when the association relation is changed such that a physical address having been associated with each logical address is associated with a different logical address, and the different logical address. A table control unit, when receiving a command to move data between logical addresses from a CPU, changes the association relation in the address translation table such that a movement-destination logical address is associated with a physical address in which the data is stored, sets change information in a movement-source logical address, and stores the movement-destination logical address as a different logical address associated with the movement-source logical address.

Abstract: A reception circuit that receives data in serial communications through a plurality of lanes includes a plurality of buffers provided for each of the plurality of lanes that each stores data received through corresponding lane, a multilane control circuit that detects the skew between the lanes, and outputs an adjustment instruction for adjusting a read address of a buffer and a deskew information indicating that a skew adjustment between which buffer the lanes is to be performed based on the detected skew, and a plurality of address control circuits provided for each of the plurality of lanes that each transmits the adjustment instruction to a corresponding buffer when receiving the deskew information, wherein the buffer that has received the adjustment instruction adjusting its read address.

Abstract: An information processing apparatus includes a reception unit configured to receive data using a plurality of lanes, a degeneration control unit configured, when a failure occurs in one of the lanes, to degenerate a predetermined number of lanes including a lane in which the failure has occurred and to cause the reception unit to receive the data using remaining lanes except for the predetermined number of the degenerated lanes among the lanes, a retraining unit configured to perform retraining to establish links in the predetermined number of the degenerated lanes, and a return control unit configured, when the links are established in the predetermined number of lanes degenerated by the retraining with the retraining unit, to cause the reception unit to receive the data using the predetermined number of the degenerated lanes and the remaining lanes.

Abstract: An information processing apparatus includes a storage device that includes a plurality of storage areas, and a processor coupled to the storage device. The processor executes a process including: first counting, among blocks each including a plurality of storage areas included in the storage device, number of transfer candidate blocks including the storage areas in which written data is invalidated; second counting, among the blocks, number of reserve blocks in which no data is written in the respective storage areas; determining whether transfer processing is to be started, in accordance with a result of comparing a count value of the first counting with a count value of the second counting; and transferring only valid data written in the respective storage areas of the transfer candidate block to the reserve block when it is determined that the transfer processing is to be started.

Abstract: An information processing apparatus includes a storage device that includes a plurality of storage areas, and a processor coupled to the storage device. The processor executes a process comprising: selecting a logical address identifying data stored in the storage device; acquiring a physical address associated with the selected logical address, from a conversion table storing therein the logical addresses and physical addresses identifying the storage areas in which the data is stored in association with each other; determining whether the stored data indicated by the acquired physical address is to be transferred; transferring the stored data to another storage area when it is determined that the data is to be transferred; and updating the physical address associated with the selected logical address in the conversion table to the physical address indicating the other storage area.

Abstract: A semiconductor circuit apparatus includes a controller configured to output a control signal, an outputting part configured to output the control signal outside of the semiconductor circuit apparatus, a condition holding part configured to hold a generating condition and an output condition of a trigger signal, a trigger signal generator configured to generate the trigger signal, if the control signal satisfies the generating condition, a delay controller configured to give a delay to the trigger signal based on the output condition, and a selector configured to be disposed between the controller and the outputting part and to selectively output the trigger signal delayed at the delay controller to the outputting part instead of the control signal output from the controller based on the output condition.

Abstract: An information processing device includes: a storage device that has a plurality of storage areas; a detection unit that carries out error detection from read data out of the storage area belonging to the storage device; a readout unit that, in a case that the detection unit detects an error, identifies an area where error occurrence is estimated including a storage area in which the data where the error is detected is written and carries out readout of data individually from each storage area in the identified area; and a movement unit that, in a case of detecting an error from the data read out by the readout unit, moves the data to another storage area.

Abstract: An information processing apparatus includes a cyclic frequency counter that updates a count value when a process that determines whether data stored in each of multiple storage areas included in NAND devices is targeted for a move has been executed on all pieces of data stored in the NAND devices. Furthermore, the information processing apparatus includes a table storing unit that stores therein, when data is stored in one of the NAND devices, the count value of the cyclic frequency counter associated with the data. Furthermore, the information processing apparatus includes a cyclic reference control unit that compares, for each data stored in the NAND devices, a value stored in the table storing unit with the count value of the cyclic frequency counter and then determines whether each piece of data is targeted for a move.

Abstract: A nonvolatile memory manages stored data by using physical addresses. By using logical addresses associated with the physical addresses, an arithmetic processing unit outputs a process instruction to be performed on data stored in the nonvolatile memory. On the basis of the process instruction output by the arithmetic processing unit, an access control unit detects an instruction to move the data stored in the nonvolatile memory. An address conversion table control unit stores therein the association relationship between the physical addresses and the logical addresses. When the access control unit detects the instruction to move the data, the address conversion table control unit changes the association relationship such that a logical address at the move destination is associated with the physical address in which the data is stored.

Abstract: A data transfer system transfers data via a plurality of signal lines and controls to select the signal lines to adapt reduction and lane reversal. The signal line control unit has a signal creation unit that creates a first selection signal when the signal lines are reduced according to the abnormal detection from the abnormal detection unit, and a signal output unit that outputs a second selection signal when a connection of the second selection signal indicating that any one or both signal line of a second pair of signal lines is changed in case of a lane reversal that connects a plurality of signal lines in a down order from a highest bit to a lowest bit of a sending device side with a plurality of signal in a up order from a highest bit to a lowest bit of a reception device side.

Abstract: Disclosed is a semiconductor device including a circuit information supply unit that supplies circuit information acquired from an outside of the semiconductor device; circuit configuration units that configure respective circuits based on the circuit information supplied from the circuit information supply unit; a specification unit that specifies whether to execute circuit configuration with respect to the circuit configuration unit; and a signal fixation unit that fixes values of signals outputted from the circuit configuration units to a designated value during a period at which the specified circuit configuration unit configures corresponding circuits based on the circuit information.

Abstract: A serial data receiver circuit apparatus to receive serial data delimited by a first bit length, the circuit apparatus includes: a serial/parallel converter circuit to convert the serial data into parallel data of a second bit length that is smaller than the first bit length; a data hold circuit to hold a plurality of parallel data; a detector circuit to detect a delimiter position in the received serial data; a detected position hold circuit to generate a select signal to select data included in the parallel data stored in the data hold circuit; and a selector circuit to select data in units of the second bit length starting from the data delimiter position based on the select signal.

Abstract: A data transfer system transfers data via a plurality of signal lines and controls to select the signal lines to adapt reduction and lane reversal. The signal line control unit has a signal creation unit that creates a first selection signal when the signal lines are reduced according to the abnormal detection from the abnormal detection unit, and a signal output unit that outputs a second selection signal when a connection of the second selection signal indicating that any one or both signal line of a second pair of signal lines is changed in case of a lane reversal that connects a plurality of signal lines in a down order from a highest bit to a lowest bit of a sending device side with a plurality of signal in a up order from a highest bit to a lowest bit of a reception device side.

Abstract: A serial data receiver circuit apparatus to receive serial data delimited by a first bit length, the circuit apparatus includes: a serial/parallel converter circuit to convert the serial data into parallel data of a second bit length that is smaller than the first bit length; a data hold circuit to hold a plurality of parallel data; a detector circuit to detect a delimiter position in the received serial data; a detected position hold circuit to generate a select signal to select data included in the parallel data stored in the data hold circuit; and a selector circuit to select data in units of the second bit length starting from the data delimiter position based on the select signal.

Abstract: A reception circuit that receives data in serial communications through a plurality of lanes includes a plurality of buffers provided for each of the plurality of lanes that each stores data received through corresponding lane, a multilane control circuit that detects the skew between the lanes, and outputs an adjustment instruction for adjusting a read address of a buffer and a deskew information indicating that a skew adjustment between which buffer the lanes is to be performed based on the detected skew, and a plurality of address control circuits provided for each of the plurality of lanes that each transmits the adjustment instruction to a corresponding buffer when receiving the deskew information, wherein the buffer that has received the adjustment instruction adjusting its read address.

Abstract: Disclosed is a semiconductor device including a circuit information supply unit that supplies circuit information acquired from an outside of the semiconductor device; circuit configuration units that configure respective circuits based on the circuit information supplied from the circuit information supply unit; a specification unit that specifies whether to execute circuit configuration with respect to the circuit configuration unit; and a signal fixation unit that fixes values of signals outputted from the circuit configuration units to a designated value during a period at which the specified circuit configuration unit configures corresponding circuits based on the circuit information.

Abstract: A data transfer system includes a transmitting device and a receiving device. The transmitting device includes a selecting unit selecting a data body to be transmitted, a transmitting unit dividing the data body and sending the data body to the plurality of signal lines, an alternative-signal-line transmitting unit sending the control data to an alternative signal line, and a signal-line selecting unit connecting the alternative signal line to an output terminal of the transmitting unit or an output terminal of the alternative signal line transmitting unit. When one of the signal lines fails, the transmission selecting unit connects the alternative signal line to the output terminal of the transmitting unit. The receiving device includes reception signal-line selecting units, each reception signal-line selecting unit selects a corresponding signal line and the alternative signal line, the receiving unit assembling the divided data body, and an alternative-signal-line receiving unit receiving the control data.

Abstract: Processing which, in conventional data transfer processing, entails the use of the common bus when performing (1) processing to confirm the interrupt state, performed via the common bus employing an interrupt register and interrupt mask register, and (2) confirmation processing performed when new frames are transferred during processing, can be performed without using the common bus. By thus reducing the frequency of access via the common bus in data transfer processing, there is no reduction in the usage ratio of the common bus by other peripheral device connected to the same common bus as certain peripheral device. As a result, the performance of the information processing terminal as a whole is not degraded. Further, even if there is currently only a single peripheral device unit connected to the common bus, degradation of the performance of the information processing terminal upon future addition of other peripheral device can be avoided.

Abstract: The invention provides an apparatus wherein, when the same main data is to be transferred to a plurality of information processing terminals, passage of the same main data or descriptor on a shared bus can be suppressed to the utmost thereby to achieve improvement of the use efficiency of the shared bus and achieve efficient data transfer. The apparatus includes a first processing section for producing transfer data and a data transfer descriptor and a second processing section for transferring the transfer data. The second processing section includes a buffer capable of temporarily storing the transfer data, a merging section capable of merging first transfer data and second transfer data produced by the first processing section and stored in advance in the buffer, and a controlling section for controlling the merging section to merge in accordance with the data transfer descriptor and performing transfer control of the merged transfer data.