Abstract: A method for optimizing a structure of an industrial product includes selecting control factors from among manufacturing parameters affecting a target characteristic, which is scheduled to be manufactured by a sequence of manufacturing processes; setting levels to the respective control factors; selecting a reference characteristic having a trade-off relation with the target characteristic from among characteristics of the structure; setting a reference value to the reference characteristic; selecting a prior adjustment factor affecting the reference characteristic; creating conditions for experiments assigning combinations of the levels to the respective control factors; determining an adjustment value of the prior adjustment factor so that each of characteristic values of the reference characteristic obtained by the experiments conforms substantially to the reference value; and determining experimental characteristic values of the target characteristic using the adjustment value.

Abstract: An field effect transistor includes a first semiconductor region, a gate electrode insulatively disposed over the first semiconductor region, source and drain electrodes between which the first semiconductor region is sandwiched, and second semiconductor regions each formed between the first semiconductor region and one of the source and drain electrodes, and having impurity concentration higher than that of the first semiconductor region, the source electrode being offset to the gate electrode in a direction in which the source electrode and the drain electrode are separated from each other with respect to a channel direction, and one of the second semiconductor regions having a thickness not more than a thickness with which the one of second semiconductor regions is completely depleted in the channel direction being in thermal equilibrium with the source electrode therewith.

Abstract: An field effect transistor includes a first semiconductor region, a gate electrode insulatively disposed over the first semiconductor region, source and drain electrodes between which the first semiconductor region is sandwiched, and second semiconductor regions each formed between the first semiconductor region and one of the source and drain electrodes, and having impurity concentration higher than that of the first semiconductor region, the source electrode being offset to the gate electrode in a direction in which the source electrode and the drain electrode are separated from each other with respect to a channel direction, and one of the second semiconductor regions having a thickness not more than a thickness with which the one of second semiconductor regions is completely depleted in the channel direction being in thermal equilibrium with the source electrode therewith.

Abstract: A method for optimizing a structure of an industrial product includes selecting control factors from among manufacturing parameters affecting a target characteristic, which is scheduled to be manufactured by a sequence of manufacturing processes; setting levels to the respective control factors; selecting a reference characteristic having a trade-off relation with the target characteristic from among characteristics of the structure; setting a reference value to the reference characteristic; selecting a prior adjustment factor affecting the reference characteristic; creating conditions for experiments assigning combinations of the levels to the respective control factors; determining an adjustment value of the prior adjustment factor so that each of characteristic values of the reference characteristic obtained by the experiments conforms substantially to the reference value; and determining experimental characteristic values of the target characteristic using the adjustment value.

Abstract: An field effect transistor includes a first semiconductor region, a gate electrode insulatively disposed over the first semiconductor region, source and drain electrodes between which the first semiconductor region is sandwiched, and second semiconductor regions each formed between the first semiconductor region and one of the source and drain electrodes, and having impurity concentration higher than that of the first semiconductor region, the source electrode being offset to the gate electrode in a direction in which the source electrode and the drain electrode are separated from each other with respect to a channel direction, and one of the second semiconductor regions having a thickness not more than a thickness with which the one of second semiconductor regions is completely depleted in the channel direction being in thermal equilibrium with the source electrode therewith.

Abstract: A method for optimizing a structure of an industrial product includes selecting control factors from among manufacturing parameters affecting a target characteristic, which is scheduled to be manufactured by a sequence of manufacturing processes; setting levels to the respective control factors; selecting a reference characteristic having a trade-off relation with the target characteristic from among characteristics of the structure; setting a reference value to the reference characteristic; selecting a prior adjustment factor affecting the reference characteristic; creating conditions for experiments assigning combinations of the levels to the respective control factors; determining an adjustment value of the prior adjustment factor so that each of characteristic values of the reference characteristic obtained by the experiments conforms substantially to the reference value; and determining experimental characteristic values of the target characteristic using the adjustment value.

Abstract: A method for optimizing a structure of an industrial product includes selecting control factors from among manufacturing parameters affecting a target characteristic, which is scheduled to be manufactured by a sequence of manufacturing processes; setting levels to the respective control factors; selecting a reference characteristic having a trade-off relation with the target characteristic from among characteristics of the structure; setting a reference value to the reference characteristic; selecting a prior adjustment factor affecting the reference characteristic; creating conditions for experiments assigning combinations of the levels to the respective control factors; determining an adjustment value of the prior adjustment factor so that each of characteristic values of the reference characteristic obtained by the experiments conforms substantially to the reference value; and determining experimental characteristic values of the target characteristic using the adjustment value.

Abstract: A semiconductor device has a first semiconductor region formed in a semiconductor substrate and having a first conductivity type due to first-conductivity-type active impurities contained in the first semiconductor region, and a second semiconductor region formed between the first semiconductor region and the surface of the semiconductor substrate and having a second conductivity type due to second-conductivity-type active impurities contained in the second semiconductor region. The second semiconductor region contains first-conductivity-type active impurities, whose concentration is zero or smaller than a quarter of a concentration of the second-conductivity-type active impurities contained in the second semiconductor region. An insulating film and a conductor are formed on the second semiconductor region. Third and fourth semiconductor regions of the second conductivity type are formed at the semiconductor surface in contact with the side faces of the second semiconductor region.

Abstract: A semiconductor integrated circuit device includes a projected semiconductor layer formed at a part of the upper surface of a semiconductor substrate; a gate insulation film formed on a first side surface of the semiconductor layer; a gate electrode formed on the gate insulation film; a first insulation film formed on a second side surface of the semiconductor layer; and a source region and a drain region formed within the semiconductor layer to sandwich the gate electrode, wherein the first insulation film has a larger thickness than that of the gate insulation film.

Abstract: There is disclosed a semiconductor device which comprises a semiconductor substrate, a pair of element isolating insulating films separately formed in the semiconductor substrate and defining an element region, a pair of impurity diffusion regions formed in the element regions and in contact with the element isolating insulating films, respectively, a channel region interposed between the pair of impurity diffusion regions, and a gate electrode formed via a gate insulating film on the channel region, the gate electrode being disposed away from end portions of the impurity diffusion regions. The gate length of the gate electrode is limited to 30 nm or less, the distance between the impurity diffusion regions and the edges of the gate electrode is respectively limited to 10 nm or less, and the distribution in lateral direction of impurity concentration in the impurity diffusion regions is limited to 1 digit/3 nm or more.

Abstract: An field effect transistor includes a first semiconductor region, a gate electrode insulatively disposed over the first semiconductor region, source and drain electrodes between which the first semiconductor region is sandwiched, and second semiconductor regions each formed between the first semiconductor region and one of the source and drain electrodes, and having impurity concentration higher than that of the first semiconductor region, the source electrode being offset to the gate electrode in a direction in which the source electrode and the drain electrode are separated from each other with respect to a channel direction, and one of the second semiconductor regions having a thickness not more than a thickness with which the one of second semiconductor regions is completely depleted in the channel direction being in thermal equilibrium with the source electrode therewith.

Abstract: There is disclosed a semiconductor device which comprises a semiconductor substrate, a pair of element isolating insulating films separately formed in the semiconductor substrate and defining an element region, a pair of impurity diffusion regions formed in the element regions and in contact with the element isolating insulating films, respectively, a channel region interposed between the pair of impurity diffusion regions, and a gate electrode formed via a gate insulating film on the channel region, the gate electrode being disposed away from end portions of the impurity diffusion regions. The gate length of the gate electrode is limited to 30 nm or less, the distance between the impurity diffusion regions and the edges of the gate electrode is respectively limited to 10 nm or less, and the distribution in lateral direction of impurity concentration in the impurity diffusion regions is limited to 1 digit/3 nm or more.

Abstract: A MIS type semiconductor device comprises a semiconductor layer provided with a recess portion having a side wall with an obtuse angle at least at a portion of the recess portion, a gate electrode formed over a bottom surface of the recess portion, with a gate insulating film interposed, a source region and a drain region formed on sides of the gate electrode with an insulating film interposed, such that boundary planes between the source region and the drain region, on one hand, and the insulating film, on the other hand, are formed in the semiconductor layer at an angle to a surface of the semiconductor layer, and wiring portions for contact with the surface of the semiconductor layer.

Abstract: There is disclosed a semiconductor device which comprises a semiconductor substrate, a pair of element isolating insulating films separately formed in the semiconductor substrate and defining an element region, a pair of impurity diffusion regions formed in the element regions and in contact with the element isolating insulating films, respectively, a channel region interposed between the pair of impurity diffusion regions, and a gate electrode formed via a gate insulating film on the channel region, the gate electrode being disposed away from end portions of the impurity diffusion regions. The gate length of the gate electrode is limited to 30 nm or less, the distance between the impurity diffusion regions and the edges of the gate electrode is respectively limited to 10 nm or less, and the distribution in lateral direction of impurity concentration in the impurity diffusion regions is limited to 1 digit/3 nm or more.

Abstract: A semiconductor device has a first semiconductor region formed in a semiconductor substrate and having a first conductivity type due to first-conductivity-type active impurities contained in the first semiconductor region, and a second semiconductor region formed between the first semiconductor region and the surface of the semiconductor substrate and having a second conductivity type due to second-conductivity-type active impurities contained in the second semiconductor region. The second semiconductor region contains first-conductivity-type active impurities, whose concentration is zero or smaller than a quarter of a concentration of the second-conductivity-type active impurities contained in the second semiconductor region. An insulating film and a conductor are formed on the second semiconductor region. Third and fourth semiconductor regions of the second conductivity type are formed at the semiconductor surface in contact with the side faces of the second semiconductor region.

Abstract: A MIS type semiconductor device comprises a semiconductor layer provided with a recess portion having a side wall with an obtuse angle at least at a portion of the recess portion, a gate electrode formed over a bottom surface of the recess portion, with a gate insulating film interposed, a source region and a drain region formed on sides of the gate electrode with an insulating film interposed, such that boundary planes between the source region and the drain region, on one hand, and the insulating film, on the other hand, are formed in the semiconductor layer at an angle to a surface of the semiconductor layer, and wiring portions for contact with the surface of the semiconductor layer.

Abstract: A semiconductor device has a first semiconductor region formed in a semiconductor substrate and having a first conductivity type due to first-conductivity-type active impurities contained in the first semiconductor region, and a second semiconductor region formed between the first semiconductor region and the surface of the semiconductor substrate and having a second conductivity type due to second-conductivity-type active impurities contained in the second semiconductor region. The second semiconductor region contains first-conductivity-type active impurities whose concentration is zero or smaller than a quarter of a concentration of the second-conductivity-type active impurities contained in the second semiconductor region. An insulating film and a conductor are formed on the second semiconductor region. Third and fourth semiconductor regions of the second conductivity type are formed at the semiconductor surface in contact with the side faces of the second semiconductor region.

Abstract: A semiconductor device has a first semiconductor region formed in a semiconductor substrate and having a first conductivity type due to first-conductivity-type active impurities contained in the first semiconductor region, and a second semiconductor region formed between the first semiconductor region and the surface of the semiconductor substrate and having a second conductivity type due to second-conductivity-type active impurities contained in the second semiconductor region. The second semiconductor region contains first-conductivity-type active impurities whose concentration is zero or smaller than a quarter of a concentration of the second-conductivity-type active impurities contained in the second semiconductor region. An insulating film and a conductor are formed on the second semiconductor region. Third and fourth semiconductor regions of the second conductivity type are formed at the semiconductor surface in contact with the side faces of the second semiconductor region.

Abstract: A semiconductor device has a first semiconductor region formed in a semiconductor substrate and having a first conductivity type due to first-conductivity-type active impurities contained in the first semiconductor region, and a second semiconductor region formed between the first semiconductor region and the surface of the semiconductor substrate and having a second conductivity type due to second-conductivity-type active impurities contained in the second semiconductor region. The second semiconductor region contains first-conductivity-type active impurities whose concentration is zero or smaller than a quarter of a concentration of the second-conductivity-type active impurities contained in the second semiconductor region. An insulating film and a conductor are formed on the second semiconductor region. Third and fourth semiconductor regions of the second conductivity type are formed at the semiconductor surface in contact with the side faces of the second semiconductor region.

Abstract: A MIS type semiconductor device comprises a semiconductor layer provided with a recess portion having a side wall with an obtuse angle at least at a portion of the recess portion, a gate electrode formed over a bottom surface of the recess portion, with a gate insulating film interposed, a source region and a drain region formed on sides of the gate electrode with an insulating film interposed, such that boundary planes between the source region and the drain region, on one hand, and the insulating film, on the other hand, are formed in the semiconductor layer at an angle to a surface of the semiconductor layer, and wiring portions for contact with the surface of the semiconductor layer.