Abstract: A signal receiver quantization circuit for an image data transmission device in which received signals are quantized correctly even if they are subjected to distortion in their time positions so that degradation of the received images is prevented. In accordance with the invention, a signal receiver includes a digital PLL circuit, a PLL control circuit for detecting the transition times of an input received signal with the digital PLL circuit being controlled in accordance with an output of the PLL control circuit, and a circuit for sampling the input signal in response to an output signal of the digital PLL circuit. In a preferred embodiment, the PLL control circuit detects the transition times of the input signal only during predetermined time slots determined in accordance with the relative phase between the input received signal and a sampling clock.

Abstract: A carrier signal recovery circuit to be used in a receiving side of an image information transmitting apparatus, such as in a facsimile system, including an N-bit counter for counting reference clock pulses for a period corresponding to 2.sup.L (L being an integer) cycle periods of the received carrier signal. A first latch holds the most significant bits from the count of the N-bit counter while a second latch holds the least significant bits from the count of the N-bit counter. A frequency divider has a frequency dividing ratio corresponding to one cycle period of the carrier signal with the value of the frequency dividing ratio being initially set by the output of the first latch circuit. An auxiliary counter receiving an input from the second latch provides an output to the frequency divider for correcting the frequency dividing ratio such that the recovered carrier signal is outputted from the frequency divider.

Abstract: A keyed AGC circuit for use in a video data transmitting device such as a facsimile system which operates stably in the presence of external noise. A processing circuit is provided for carrying out digital processing determining whether the synchronizing signal level at an output terminal of the AGC circuit is higher or lower than a pre-set reference level. A multi-stage digital attenuator is controlled in response to outputs of the processing circuit to set the attenuation level. Control of the multi-stage digital attenuator can start with either the most significant bit position of the attenuator prior to video data transmission or with a least significant bit position of the attenuator in a synchronization period after video data transmission has been started.