Patents by Inventor Kazumoto Tamura

Kazumoto Tamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8942946
    Abstract: Provided is a test apparatus that tests a device under test, comprising a test unit that sends and receives signals to and from the device under test; a control apparatus that controls the test unit; and a relay apparatus that relays between the control apparatus and the test unit. The relay apparatus includes a first communicating section that receives a command from the control apparatus to the relay apparatus and transmits the command to the test unit; a second communicating section that receives a return command that is transmitted back to the relay apparatus by the test unit that received the command; and an executing section that executes a process designated by the return command, in response to the second communicating section receiving the return command.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: January 27, 2015
    Assignee: Advantest Corporation
    Inventor: Kazumoto Tamura
  • Patent number: 8805634
    Abstract: A test apparatus that tests a device under test, including a control apparatus that controls testing of the device under test, a test unit that sends and receives signals to and from the device under test, and a buffer section that buffers access requests transmitted from the control apparatus to the test unit and, prior to completion of a write request to a predetermined buffer control address from the control apparatus, issues previously buffered access requests to the test unit side.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: August 12, 2014
    Assignee: Advantest Corporation
    Inventor: Kazumoto Tamura
  • Publication number: 20130266044
    Abstract: To lower the cost of an apparatus. A test apparatus including a first communication device and a second communication device is provided. The first communication device includes a first transmitting unit that transmits, to the second communication device, a signal including a control code of a code value corresponding to a transmission rate to be used in communication between the first communication device and the second communication device when the communication is not established therebetween, and the second communication device includes: a first receiving unit that receives a signal from the first communication device; and a specifying unit that specifies the transmission rate corresponding to the control code included in the signal transmitted from the first communication device when the communication is not established between the first communication device and the second communication device.
    Type: Application
    Filed: April 18, 2013
    Publication date: October 10, 2013
    Inventor: Kazumoto TAMURA
  • Publication number: 20130254595
    Abstract: An instruction is assuredly transmitted. A test apparatus that tests a device under test, includes a test unit that tests a device under test by exchanging a signal with the device under test, a control apparatus that controls the test unit; and a relay apparatus that relays communication between the test unit and the control apparatus, where the control apparatus transmits an instruction to be given to the test unit a plurality of times to the test unit, and the test unit receives the instruction transmitted the plurality of times from the control apparatus, and executes the instruction once.
    Type: Application
    Filed: April 9, 2013
    Publication date: September 26, 2013
    Applicant: ADVANTEST CORPORATION
    Inventor: Kazumoto TAMURA
  • Publication number: 20130244568
    Abstract: A test apparatus ensures to establish communication. A test apparatus including a first communication apparatus and a second communication apparatus, where the transmitting section of the first communication apparatus transmits the first linkup code to the receiving section of the second communication apparatus, the transmitting section of the second communication apparatus transmits, instead of the first linkup code, the second linkup code in response to communication having being established between the receiving section of the second communication apparatus and the transmitting section of the first communication apparatus, and the receiving section of the first communication apparatus starts communicating with the transmitting section of the relay apparatus, in response to communication having being established with the transmitting section of the relay apparatus and reception of the second linkup code from the transmitting section of the relay apparatus.
    Type: Application
    Filed: April 12, 2013
    Publication date: September 19, 2013
    Applicant: ADVANTEST CORPORATION
    Inventor: Kazumoto TAMURA
  • Patent number: 8155897
    Abstract: Provided is a semiconductor test apparatus that tests a device under test, comprising a test unit that tests a device under test; and a serial transmitting section that transmits transmission data back and forth between the test unit and a control section controlling the test unit. The serial transmitting section includes a data sending section that sends a plurality of pieces of the transmission data in a predetermined order; a resending control section that resends the transmission data; and an expected acknowledgement ID storage section that stores an expected acknowledgement ID indicating identification data that is expected to be attached to an acknowledgement signal received on a transmission side. The resending control section judges whether resending is necessary based on (i) whether resend count information indicates that a piece of transmission data is resent data and (ii) the expected acknowledgment ID in the expected acknowledgement ID storage section.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: April 10, 2012
    Assignee: Advantest Corporation
    Inventors: Masaaki Kosugi, Kazumoto Tamura
  • Publication number: 20110282616
    Abstract: Provided is a test apparatus that tests a device under test, comprising a control apparatus that controls testing of the device under test; a test unit that sends and receives signals to and from the device under test; and a buffer section that buffers access requests transmitted from the control apparatus to the test unit and, prior to completion of a write request to a predetermined buffer control address from the control apparatus, issues previously buffered access requests to the test unit side.
    Type: Application
    Filed: November 12, 2010
    Publication date: November 17, 2011
    Applicant: ADVANTEST CORPORATION
    Inventor: Kazumoto TAMURA
  • Publication number: 20110208465
    Abstract: Provided is a test apparatus that tests a device under test, comprising a test unit that sends and receives signals to and from the device under test; a control apparatus that controls the test unit; and a relay apparatus that relays between the control apparatus and the test unit. The relay apparatus includes a first communicating section that receives a command from the control apparatus to the relay apparatus and transmits the command to the test unit; a second communicating section that receives a return command that is transmitted back to the relay apparatus by the test unit that received the command; and an executing section that executes a process designated by the return command, in response to the second communicating section receiving the return command.
    Type: Application
    Filed: November 12, 2010
    Publication date: August 25, 2011
    Applicant: ADVANTEST CORPORATION
    Inventor: Kazumoto TAMURA
  • Publication number: 20110208448
    Abstract: Provided is a test apparatus that tests a device under test, comprising a plurality of processing sections that each send and receive signals to and from the device under test; a control apparatus that controls the processing sections; and an interrupt control section that notifies the control apparatus concerning interrupt requests generated by the processing sections, wherein, when an interrupt request is received from a processing section while the interrupt control section is in an interrupt enable state, the interrupt control section notifies the control apparatus concerning the interrupt and transitions to an interrupt disable state; when an interrupt request is received from the processing section while the interrupt control section is in the interrupt disable state, the interrupt control section does not notify the control apparatus concerning the interrupt; and when instructions are received from the control apparatus while the interrupt control section is in the interrupt disable state, the interrup
    Type: Application
    Filed: November 12, 2010
    Publication date: August 25, 2011
    Applicant: ADVANTEST CORPORATION
    Inventor: Kazumoto TAMURA
  • Publication number: 20110196638
    Abstract: Provided is a test apparatus that tests a device under test, comprising a test unit that sends and receives signals to and from the device under test; a control apparatus that controls the test unit; and a relay apparatus that relays between the control apparatus and the test unit. The relay apparatus includes a read issuing section that receives a command from the control apparatus and issues a read command for reading read data stored at an address designated by the control apparatus in a storage apparatus of the test unit; a buffer section that buffers the read data transmitted from the test unit in response to the read command; and a data transmitting section that receives the read command from the control apparatus and sends back the read data buffered in the buffer section.
    Type: Application
    Filed: November 9, 2010
    Publication date: August 11, 2011
    Applicant: ADVANTEST CORPORATION
    Inventor: Kazumoto Tamura
  • Publication number: 20100191895
    Abstract: There is a system comprising a requesting device including a block generating section which generates an access information block storing access information including a target address of an access target and an access command indicating content to be executed for the access target in each of a plurality of accesses, and a block transmitting section which transmits the generated access information block to a relay apparatus, the relay apparatus including a block receiving section which receives the access information block from the requesting device and an access issuing section which sequentially issues corresponding access to a responding device on the basis of the access information included in the transmitted access information block, and the responding device including an access receiving section which receives each access corresponding to the access information included in the access information block from the relay apparatus and an access processing section which executes an access process for a storage
    Type: Application
    Filed: February 24, 2010
    Publication date: July 29, 2010
    Applicant: ADVANTEST CORPORATION
    Inventor: Kazumoto TAMURA
  • Publication number: 20100153034
    Abstract: Provided is a semiconductor test apparatus that tests a device under test, comprising a test unit that tests a device under test; and a serial transmitting section that transmits transmission data back and forth between the test unit and a control section controlling the test unit. The serial transmitting section includes a data sending section that sends a plurality of pieces of the transmission data in a predetermined order; a resending control section that resends the transmission data; and an expected acknowledgement ID storage section that stores an expected acknowledgement ID indicating identification data that is expected to be attached to an acknowledgement signal received on a transmission side. The resending control section judges whether resending is necessary based on (i) whether resend count information indicates that a piece of transmission data is resent data and (ii) the expected acknowledgment ID in the expected acknowledgement ID storage section.
    Type: Application
    Filed: December 16, 2008
    Publication date: June 17, 2010
    Applicant: ADVANTEST CORPORATION
    Inventors: Masaaki Kosugi, Kazumoto Tamura