Patents by Inventor Kazunaga Onishi
Kazunaga Onishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12148631Abstract: A method for manufacturing a fin-integrated semiconductor module includes: clamping a fin-integrated heat-dissipation base using a level different jig while making the heat-dissipation base vary in height; and soldering a semiconductor assembly onto the heat-dissipation base. A semiconductor module includes a fin-integrated heat-dissipation base and a semiconductor assembly provided on the heat-dissipation base. A bending width of the heat-dissipation base is 200 ?m or less.Type: GrantFiled: November 1, 2022Date of Patent: November 19, 2024Assignee: FUJI ELECTRIC CO., LTD.Inventors: Kazunaga Onishi, Takashi Masuzawa, Hiromichi Gohara
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Patent number: 11935774Abstract: Provided is an assembly jig set of semiconductor module having a plurality of semiconductor chips, the assembly jig set comprising: a first outer frame jig; and a plurality of inner piece jigs positioned by the first outer frame jig and each having a sectioned shape corresponding to the first outer frame jig, wherein one of the inner piece jigs has a plurality of opening portions for positioning the semiconductor chips. A manufacturing method of a semiconductor module using an assembly jig set is provided.Type: GrantFiled: May 23, 2022Date of Patent: March 19, 2024Assignee: FUJI ELECTRIC CO., LTD.Inventors: Kazunaga Onishi, Takeshi Yokoyama, Masaki Maruyama
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Publication number: 20230046160Abstract: A method for manufacturing a fin-integrated semiconductor module includes: clamping a fin-integrated heat-dissipation base using a level different jig while making the heat-dissipation base vary in height; and soldering a semiconductor assembly onto the heat-dissipation base. A semiconductor module includes a fin-integrated heat-dissipation base and a semiconductor assembly provided on the heat-dissipation base. A bending width of the heat-dissipation base is 200 ?m or less.Type: ApplicationFiled: November 1, 2022Publication date: February 16, 2023Inventors: Kazunaga ONISHI, Takashi MASUZAWA, Hiromichi GOHARA
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Patent number: 11501980Abstract: A method for manufacturing a fin-integrated semiconductor module includes: clamping a fin-integrated heat-dissipation base using a level different jig while making the heat-dissipation base vary in height; and soldering a semiconductor assembly onto the heat-dissipation base. A semiconductor module includes a fin-integrated heat-dissipation base and a semiconductor assembly provided on the heat-dissipation base. A bending width of the heat-dissipation base is 200 ?m or less.Type: GrantFiled: March 26, 2020Date of Patent: November 15, 2022Assignee: FUJI ELECTRIC CO., LTD.Inventors: Kazunaga Onishi, Takashi Masuzawa, Hiromichi Gohara
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Publication number: 20220285194Abstract: Provided is an assembly jig set of semiconductor module having a plurality of semiconductor chips, the assembly jig set comprising: a first outer frame jig; and a plurality of inner piece jigs positioned by the first outer frame jig and each having a sectioned shape corresponding to the first outer frame jig, wherein one of the inner piece jigs has a plurality of opening portions for positioning the semiconductor chips. A manufacturing method of a semiconductor module using an assembly jig set is provided.Type: ApplicationFiled: May 23, 2022Publication date: September 8, 2022Inventors: Kazunaga ONISHI, Takeshi YOKOYAMA, Masaki MARUYAMA
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Patent number: 11355373Abstract: Provided is an assembly jig set of semiconductor module having a plurality of semiconductor chips, the assembly jig set comprising: a first outer frame jig; and a plurality of inner piece jigs positioned by the first outer frame jig and each having a sectioned shape corresponding to the first outer frame jig, wherein one of the inner piece jigs has a plurality of opening portions for positioning the semiconductor chips. A manufacturing method of a semiconductor module using an assembly jig set is provided.Type: GrantFiled: February 24, 2020Date of Patent: June 7, 2022Assignee: FUJI ELECTRIC CO., LTD.Inventors: Kazunaga Onishi, Takeshi Yokoyama, Masaki Maruyama
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Patent number: 11107787Abstract: A member for semiconductor device includes a metal portion configured to be bonded to another member by solder, and a treated coating covering a surface of the metal portion, the treated coating including a treatment agent. The treated coating vaporizes at a temperature lower than or equal to a solidus temperature of the solder.Type: GrantFiled: November 8, 2018Date of Patent: August 31, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventors: Shinji Sano, Yoshihiro Kodaira, Masayuki Soutome, Kazunaga Onishi
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Publication number: 20200365419Abstract: A method for manufacturing a fin-integrated semiconductor module includes: clamping a fin-integrated heat-dissipation base using a level different jig while making the heat-dissipation base vary in height; and soldering a semiconductor assembly onto the heat-dissipation base. A semiconductor module includes a fin-integrated heat-dissipation base and a semiconductor assembly provided on the heat-dissipation base. A bending width of the heat-dissipation base is 200 ?m or less.Type: ApplicationFiled: March 26, 2020Publication date: November 19, 2020Inventors: Kazunaga ONISHI, Takashi MASUZAWA, Hiromichi GOHARA
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Publication number: 20200335375Abstract: Provided is an assembly jig set of semiconductor module having a plurality of semiconductor chips, the assembly jig set comprising: a first outer frame jig; and a plurality of inner piece jigs positioned by the first outer frame jig and each having a sectioned shape corresponding to the first outer frame jig, wherein one of the inner piece jigs has a plurality of opening portions for positioning the semiconductor chips. A manufacturing method of a semiconductor module using an assembly jig set is provided.Type: ApplicationFiled: February 24, 2020Publication date: October 22, 2020Inventors: Kazunaga ONISHI, Takeshi YOKOYAMA, Masaki MARUYAMA
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Publication number: 20190081020Abstract: A member for semiconductor device includes a metal portion configured to be bonded to another member by solder, and a treated coating covering a surface of the metal portion, the treated coating including a treatment agent. The treated coating vaporizes at a temperature lower than or equal to a solidus temperature of the solder.Type: ApplicationFiled: November 8, 2018Publication date: March 14, 2019Inventors: Shinji SANO, Yoshihiro KODAIRA, Masayuki SOUTOME, Kazunaga ONISHI
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Patent number: 10153246Abstract: There is provided a method for producing a member for semiconductor device which can reduce generation of a large number of voids in a solder-bonded portion without increasing production cost. The method includes the step of preparing a first member including a metal portion capable of being bonded by solder and the step of coating the surface of the metal portion of the first member with a treatment agent to form a treated coating which vaporizes at a temperature lower than or equal to the solidus temperature of the solder.Type: GrantFiled: November 30, 2016Date of Patent: December 11, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Shinji Sano, Yoshihiro Kodaira, Masayuki Soutome, Kazunaga Onishi
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Patent number: 10002845Abstract: In a soldering method for Ag-containing lead-free solders to be soldered to an Ag-containing member, void generation is prevented and solder wettability is improved. The soldering method for Ag-containing lead-free solders of the present invention is a soldering method for Ag-containing lead-free solders includes a first step of bringing a lead-free solder having a composition that contains Ag that a relation between a concentration C (mass %) of Ag contained in an Sn—Ag-based lead-free solder before soldering of a mass M(g) and an elution amount B(g) of Ag contained in the Ag-containing member becomes 1.0 mass %?(M×C+B)×100/(M+B)?4.6 mass % and that the balance consists of Sn and unavoidable impurities into contact with the Ag-containing member, a second step of heating and melting the lead-free solder, and a third step of cooling the lead-free solder.Type: GrantFiled: September 26, 2016Date of Patent: June 19, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Hirohiko Watanabe, Shunsuke Saito, Masahiro Ono, Takashi Watanabe, Shinji Sano, Kazunaga Onishi
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Patent number: 9876293Abstract: A semiconductor device having a tubular part is able to prevent the solder from spattering when soldering the tubular part. The semiconductor device has a insulated substrate that has a circuit layer on a front surface thereof, a tubular part that is soldered to the circuit layer, and an external terminal that is inserted into the tubular part and connected electrically to the tubular part. The tubular part has a cylinder portion and a flange portion that is connected to one longitudinal end of the cylinder portion. The flange portion has a first projection, a second projection and a third projection that face the circuit layer. The distance between the first projection and the second projection, the distance between the second projection and the third projection, and the distance between the third projection and the first projection each are greater than the inner diameter of the cylinder portion.Type: GrantFiled: May 10, 2016Date of Patent: January 23, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Kazunaga Onishi, Rikihiro Maruyama, Wan Azha Bin Wan Mat
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Publication number: 20170207187Abstract: There is provided a method for producing a member for semiconductor device which can reduce generation of a large number of voids in a solder-bonded portion without increasing production cost. The method includes the step of preparing a first member including a metal portion capable of being bonded by solder and the step of coating the surface of the metal portion of the first member with a treatment agent to form a treated coating which vaporizes at a temperature lower than or equal to the solidus temperature of the solder.Type: ApplicationFiled: November 30, 2016Publication date: July 20, 2017Inventors: Shinji SANO, Yoshihiro KODAIRA, Masayuki SOUTOME, Kazunaga ONISHI
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Patent number: 9595491Abstract: An apparatus for a manufacturing semiconductor device including a plate member and a joint member. The apparatus includes a plate-type tool having the plate member mounted thereon, a first fixing tool and a second fixing tool having an inclined surface for abutting an upper edge of an end part in a width direction of plate member. The second fixing tool is fixed onto the plate-type tool adjacent to the end part. An ultrasonic horn applies ultrasonic vibration in the width direction of plate member while pressing the joint member toward the plate member.Type: GrantFiled: September 9, 2015Date of Patent: March 14, 2017Assignee: FUJI ELECTRIC CO., LTD.Inventors: Yosuke Miyazawa, Kazunaga Onishi
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Publication number: 20170012018Abstract: In a soldering method for Ag-containing lead-free solders to be soldered to an Ag-containing member, void generation is prevented and solder wettability is improved. The soldering method for Ag-containing lead-free solders of the present invention is a soldering method for Ag-containing lead-free solders includes a first step of bringing a lead-free solder having a composition that contains Ag that a relation between a concentration C (mass %) of Ag contained in an Sn—Ag-based lead-free solder before soldering of a mass M(g) and an elution amount B(g) of Ag contained in the Ag-containing member becomes 1.0 mass %?(M×C+B)×100/(M+B)?4.6 mass % and that the balance consists of Sn and unavoidable impurities into contact with the Ag-containing member, a second step of heating and melting the lead-free solder, and a third step of cooling the lead-free solder.Type: ApplicationFiled: September 26, 2016Publication date: January 12, 2017Applicant: FUJI ELECTRIC CO., LTD.Inventors: Hirohiko WATANABE, Shunsuke SAITO, Masahiro ONO, Takashi WATANABE, Shinji SANO, Kazunaga ONISHI
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Publication number: 20160380366Abstract: A semiconductor device having a tubular part is able to prevent the solder from spattering when soldering the tubular part. The semiconductor device has a insulated substrate that has a circuit layer on a front surface thereof, a tubular part that is soldered to the circuit layer, and an external terminal that is inserted into the tubular part and connected electrically to the tubular part. The tubular part has a cylinder portion and a flange portion that is connected to one longitudinal end of the cylinder portion. The flange portion has a first projection, a second projection and a third projection that face the circuit layer. The distance between the first projection and the second projection, the distance between the second projection and the third projection, and the distance between the third projection and the first projection each are greater than the inner diameter of the cylinder portion.Type: ApplicationFiled: May 10, 2016Publication date: December 29, 2016Applicant: FUJI ELECTRIC CO., LTD.Inventors: Kazunaga ONISHI, Rikihiro MARUYAMA, Wan Azha BIN WAN MAT
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Patent number: 9466509Abstract: A method of manufacturing a semiconductor device, includes preparing a molding die for molding a resin case for a semiconductor device, the molding die having protrusions to fix each of a plurality of terminals having a leg portion in a predetermined position; conforming and holding each of the plurality of terminals to the corresponding protrusions in the molding die; and injecting resin into the molding die to integrally mold the plurality of terminals and the resin case.Type: GrantFiled: May 18, 2015Date of Patent: October 11, 2016Assignee: FUJI ELECTRIC CO., LTD.Inventors: Kazunaga Onishi, Rikihiro Maruyama, Masafumi Tezuka, Masahiro Kikuchi
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Publication number: 20160093564Abstract: An apparatus for a manufacturing semiconductor device including a plate member and a joint member. The apparatus includes a plate-type tool having the plate member mounted thereon, a first fixing tool and a second fixing tool having an inclined surface for abutting an upper edge of an end part in a width direction of plate member. The second fixing tool is fixed onto the plate-type tool adjacent to the end part. An ultrasonic horn applies ultrasonic vibration in the width direction of plate member while pressing the joint member toward the plate member.Type: ApplicationFiled: September 9, 2015Publication date: March 31, 2016Applicant: FUJI ELECTRIC CO., LTD.Inventors: Yosuke MIYAZAWA, Kazunaga ONISHI
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Patent number: 9171768Abstract: A semiconductor device includes an insulating substrate joined with a semiconductor chip, a case covering a surface of the insulating substrate where the semiconductor chip is joined, and a control terminal in which one end portion is electrically connected to the semiconductor chip, and another end portion passes through the case and is exposed to outside of the case. A portion of the control terminal exposed to the outside of the case includes a cut-out section where a part of the exposed portion is cut out, and a blocking section formed by bending a portion surrounded by the cut-out section and remaining on the control terminal. The blocking section contacts the case from the outside of the case and blocks a movement of the control terminal.Type: GrantFiled: September 3, 2012Date of Patent: October 27, 2015Assignee: FUJI ELECTRIC CO., LTD.Inventors: Yoshikazu Takamiya, Yoshihiro Kodaira, Kazunaga Onishi