Patents by Inventor Kazunari Aoyama

Kazunari Aoyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9857411
    Abstract: An electronic device including a printed circuit board has a degradation detection circuit that detects degradation of the printed circuit board at a plurality of different degradation levels, and a warning output unit that outputs a warning in accordance with the degradation level detected by the degradation detection circuit.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: January 2, 2018
    Assignee: FANUC Corporation
    Inventors: Kazunari Aoyama, Kunitaka Komaki, Yasumichi Sakoda
  • Patent number: 9753688
    Abstract: Provided is a motor control system of a numerical controller that can instruct a plurality of motors and display data on a display device by means of a single serial bus. An amplifier which controls the motor drives the motor based on a motor command received from the numerical controller via the serial bus. The display device display data on a screen based on display data received from the numerical controller via the serial bus.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: September 5, 2017
    Assignee: FANUC Corporation
    Inventors: Kazunari Aoyama, Kunitaka Komaki
  • Publication number: 20150219713
    Abstract: An electronic device including a printed circuit board has a degradation detection circuit that detects degradation of the printed circuit board at a plurality of different degradation levels, and a warning output unit that outputs a warning in accordance with the degradation level detected by the degradation detection circuit.
    Type: Application
    Filed: February 3, 2015
    Publication date: August 6, 2015
    Inventors: Kazunari AOYAMA, Kunitaka KOMAKI, Yasumichi SAKODA
  • Publication number: 20150077031
    Abstract: A numerical control device including a numerical controller, a robot controller, a servo control module and an I/O control module connected to the numerical controller and the robot controller, and an amplifier connecting bus connecting the servo control module and a servo amplifier, and an I/O device connecting bus connecting an I/O control module and an I/O interface device. The machine-tool-side and robot-side servo amplifiers are daisy-chained and the machine-tool-side and robot-side I/O interface devices are daisy-chained.
    Type: Application
    Filed: September 11, 2014
    Publication date: March 19, 2015
    Applicant: FANUC CORPORATION
    Inventors: Naoki Sugitani, Kazunari Aoyama
  • Publication number: 20150054839
    Abstract: Provided is a motor control system of a numerical controller that can instruct a plurality of motors and display data on a display device by means of a single serial bus. An amplifier which controls the motor drives the motor based on a motor command received from the numerical controller via the serial bus. The display device display data on a screen based on display data received from the numerical controller via the serial bus.
    Type: Application
    Filed: August 12, 2014
    Publication date: February 26, 2015
    Inventors: Kazunari AOYAMA, Kunitaka KOMAKI
  • Publication number: 20140316565
    Abstract: A numerical controller includes a numerical control unit for executing a numerical control program, a robot control unit for executing a robot program, a multicore processor having a plurality of cores, and a peripheral control LSI. The numerical control unit is assigned to one of the cores of the multicore processor and the robot control unit is assigned to one of the others. The multicore processor is connected to an internal bus of the numerical controller via the peripheral control LSI.
    Type: Application
    Filed: April 16, 2014
    Publication date: October 23, 2014
    Applicant: FANUC Corporation
    Inventor: Kazunari AOYAMA
  • Publication number: 20140042950
    Abstract: A numerical controller includes a multicore processor, an integrated peripheral control LSI, a motor control section and an amplifier interface section. The multicore processor has two cores. One is assigned as a numerical control section processor core, and the other is assigned as a programmable machine controller section processor core. The motor control section is composed of a motor control section processor and a peripheral control LSI.
    Type: Application
    Filed: July 31, 2013
    Publication date: February 13, 2014
    Applicant: FANUC Corporation
    Inventors: Kazunari AOYAMA, Kunitaka KOMAKI
  • Patent number: 8055812
    Abstract: An amplifier (unit) linked via a daisy type serial bus sends a transmission start signal SC and then sends the local data DATAn. If data from an amplifier at the downstream side is not received before transmission of the local data DATAn is completed, the delimit of the data from each amplifier is changed by adding an idle time data TIDD.
    Type: Grant
    Filed: November 19, 2007
    Date of Patent: November 8, 2011
    Assignee: Fanuc Ltd
    Inventors: Kazunari Aoyama, Kunitaka Komaki, Yasuharu Aizawa
  • Patent number: 8054028
    Abstract: A table containing correspondence between “n” and “m” is set in a control circuit of a servo control system so that the current command data in the m-th (m=1, 2, 3 . . . ) current command register is assigned to the n-th (n=1, 2, 3 . . . ) servo amplifier. When data is specified in this table to satisfy “n=m”, the current command data in the n-th current command register is passed to the n-th servo amplifier. When “m=1” is set for “n=1” and “m=1” is set for “n=2” in this table, the current command data stored in the first current command register is passed to the first and second servo amplifiers.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: November 8, 2011
    Assignee: FANUC Ltd
    Inventors: Kazunari Aoyama, Kunitaka Komaki, Yasuharu Aizawa
  • Patent number: 7839110
    Abstract: A motor control system includes a first-type amplifier that receives a PWM instruction, a second-type amplifier that receives a positional instruction, a numerical control device, and a serial bus. The numerical control device includes a first processor that calculates a positional instruction of a motor, a DSP that calculates a PWM instruction of the first-type amplifier from the positional instruction, and a serial bus control circuit that outputs the PWM instruction of the first-type amplifier and the positional instruction of the second-type amplifier to the serial bus. The first-type amplifier generates a drive current signal of a motor directly from the received PWM instruction. The second-type amplifier includes a third processor that calculates a PWM instruction from the received positional instruction.
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: November 23, 2010
    Assignee: Fanuc Ltd
    Inventors: Kazunari Aoyama, Kunitaka Komaki, Yasuharu Aizawa
  • Patent number: 7653768
    Abstract: A data transfer method for connecting a master unit on an upstream side and a plurality of slave units on an downstream side in series with serial bus by a daisy chain system and transferring data having an appended error check code or error correction code between a data transmitter and a data receiver, the data transfer method including: transferring the data flowing in the serial bus in the slave unit from the data transmitter to the data receiver without performing an error check or error correction; performing an error check of the data in a circuit provided in the slave unit aside from a circuit in which the data flow; and informing a result of the error check to the master unit individually by the slave unit, which has performed the error check of the data.
    Type: Grant
    Filed: August 23, 2007
    Date of Patent: January 26, 2010
    Assignee: Fanuc Ltd
    Inventors: Kazunari Aoyama, Kunitaka Komaki, Masahiro Miura
  • Publication number: 20090195206
    Abstract: A table containing correspondence between “n” and “m” is set in a control circuit of a servo control system so that the current command data in the m-th (m=1, 2, 3 . . . ) current command register is assigned to the n-th (n=1, 2, 3 . . . ) servo amplifier. When data is specified in this table to satisfy “n=m”, the current command data in the n-th current command register is passed to the n-th servo amplifier. When “m=1” is set for “n=1” and “m=1” is set for “n=2” in this table, the current command data stored in the first current command register is passed to the first and second servo amplifiers.
    Type: Application
    Filed: November 13, 2008
    Publication date: August 6, 2009
    Applicant: FANUC LTD
    Inventors: Kazunari AOYAMA, Kunitaka KOMAKI, Yasuharu AIZAWA
  • Patent number: 7525263
    Abstract: A master unit and a plurality of slave units are connected by way of a communication path. The master unit sends to the slave units timing signals generated by its own cycle signal generator by way of a communication path. The slave units determine the cycle difference and the phase difference between a timing signal generated by its own cycle signal generator and the timing signal sent from the master unit and, in accordance therewith, determine a cycle adjustment amount. The cycle signal generators of the slave units adjust the timing signal cycle based on the cycle adjustment amount.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: April 28, 2009
    Assignee: Fanuc Ltd
    Inventors: Kazunari Aoyama, Minoru Nakamura, Takaaki Komatsu
  • Patent number: 7519113
    Abstract: Noise detection is performed by using the output of the phase comparator that the PLL comprises. The phase comparator outputs a signal that is based on the phase difference between the output of the voltage controlled oscillator and the reference signal. The phase difference reflects the effect of noise on the PLL and, in addition to the characteristics of the noise itself, such as the wave height value of the noise and the frequency component thereof, reflects the tolerance of the PLL to noise, whereby the level of risk that the system can actually be caused to malfunction can be judged.
    Type: Grant
    Filed: January 19, 2005
    Date of Patent: April 14, 2009
    Assignee: Fanuc Ltd
    Inventors: Kazunari Aoyama, Minoru Nakamura, Masahiro Miura
  • Patent number: 7432674
    Abstract: A transmission path delay is set in a shift setting register. A slave unit generates a PRE_ITP signal in response to a timing signal (ITP signal) issued by a master unit. The phase difference between this PRE_ITP signal and the ITP signal unique to the slave unit is loaded into a period modification counter. A timer corrects a reference value, outputs position/speed control period signals (SYN signals) and counts down the period modification counter with these SYN signals until the period modification counter reaches zero. Furthermore, the ITP signal unique to the slave unit is outputted every time a predetermined number of the SYN signals are outputted.
    Type: Grant
    Filed: March 3, 2006
    Date of Patent: October 7, 2008
    Assignee: Fanuc Ltd.
    Inventors: Kazunari Aoyama, Kunitaka Komaki, Minoru Nakamura, Takaaki Komatsu
  • Publication number: 20080238351
    Abstract: A motor control system in which one numerical control device controls a first-type amplifier without a DSP and a second-type amplifier with a DSP, and the cost of which has been reduced by reducing the number of interface circuits (serial bus control circuits) to be provided in the numerical control device has been disclosed.
    Type: Application
    Filed: March 4, 2008
    Publication date: October 2, 2008
    Applicant: FANUC LTD
    Inventors: Kazunari AOYAMA, Kunitaka KOMAKI, Yasuharu AIZAWA
  • Patent number: 7428686
    Abstract: A controller has a plurality of modules connected to each other via buses. On the transmitter side of each module, detection/correction code generation circuit for address/command and detection/correction code generation circuits for each kind of data are switched over according to information to be transmitted by a transmitter selection circuit, and then the data is transmitted with ECC code attached. On the receiver side, a receiver selection circuit selectively switches over an error detection/correction circuit for address/command and error detection/correction circuits for each kind of data to detect and correct errors.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: September 23, 2008
    Assignee: Fanuc Ltd
    Inventors: Kazunari Aoyama, Minoru Nakamura, Yutaka Sakai
  • Publication number: 20080123723
    Abstract: An amplifier (unit) linked via a daisy type serial bus sends a transmission start signal SC and then sends the local data DATAn. If data from an amplifier at the downstream side is not received before transmission of the local data DATAn is completed, the delimit of the data from each amplifier is changed by adding an idle time data TIDD.
    Type: Application
    Filed: November 19, 2007
    Publication date: May 29, 2008
    Applicant: FANUC LTD
    Inventors: Kazunari Aoyama, Kunitaka Komaki, Yasuharu Aizawa
  • Publication number: 20080052417
    Abstract: A data transfer method for connecting a master unit on an upstream side and a plurality of slave units on an downstream side in series with serial bus by a daisy chain system and transferring data having an appended error check code or error correction code between a data transmitter and a data receiver, the data transfer method including: transferring the data flowing in the serial bus in the slave unit from the data transmitter to the data receiver without performing an error check or error correction; performing an error check of the data in a circuit provided in the slave unit aside from a circuit in which the data flow; and informing a result of the error check to the master unit individually by the slave unit, which has performed the error check of the data.
    Type: Application
    Filed: August 23, 2007
    Publication date: February 28, 2008
    Applicant: FANUC LTD
    Inventors: Kazunari AOYAMA, Kunitaka KOMAKI, Masahiro MIURA
  • Publication number: 20080013279
    Abstract: A heat sink including a base and a plurality of upright heat-radiating projections provided on the base. The heat-radiating projections include a first projection having a first rigidity, and a second projection having at least a second rigidity partially lower than the first rigidity. The second projection is located along an outer periphery of an array or configuration of the plurality of heat-radiating projections on the base.
    Type: Application
    Filed: June 26, 2007
    Publication date: January 17, 2008
    Applicant: FANUC LTD
    Inventors: Kazunari AOYAMA, Minoru NAKAMURA, Masahiro MIURA