Patents by Inventor Kazunari Horikawa

Kazunari Horikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuit device and wiring arranging method thereof
    Patent number: 6962868
    Abstract: Even where an I/O cell requiring good characteristics is alloted to an I/O slot corresponding to the uppermost standard pattern wiring, a pad can be connected to the I/O slot by forming rewiring in the chip outermost peripheral area.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: November 8, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinsuke Sakamoto, Yasuo Inbe, Masakazu Yaginuma, Kazunari Horikawa, Toshikazu Sei
  • Semiconductor integrated circuit device and wiring arranging method thereof
    Patent number: 6844630
    Abstract: Even where an I/O cell requiring good characteristics is alloted to an I/O slot corresponding to the uppermost standard pattern wiring, a pad can be connected to the I/O slot by forming rewiring in the chip outermost peripheral area.
    Type: Grant
    Filed: February 25, 2002
    Date of Patent: January 18, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinsuke Sakamoto, Yasuo Inbe, Masakazu Yaginuma, Kazunari Horikawa, Toshikazu Sei
  • Semiconductor integrated circuit device and wiring arranging method thereof
    Publication number: 20040227161
    Abstract: Even where an I/O cell requiring good characteristics is alloted to an I/O slot corresponding to the uppermost standard pattern wiring, a pad can be connected to the I/O slot by forming rewiring in the chip outermost peripheral area.
    Type: Application
    Filed: June 30, 2004
    Publication date: November 18, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shinsuke Sakamoto, Yasuo Inbe, Masakazu Yaginuma, Kazunari Horikawa, Toshikazu Sei
  • LSI design verification apparatus, LSI design verification method, and LSI design verification program
    Publication number: 20030125920
    Abstract: A computer implemented method for design verification using logical simulation of a circuit description having a plurality of hierarchies from top to bottom in accordance with abstraction of circuit components, which have an arithmetic and logic function, reads the circuit description and analyzes signal connection topologies between the hierarchies of the circuit description from top to bottom. The method stores the data of the signal connection topologies. The method reads properties of target modules implemented by the circuit components in the circuit description. The method extracts a property part having a signal communicating between the target modules. The method extracts an output operation property, defining output operation of an output side module, and an expecting operation property, defining an expecting operation of an input side module among the properties of the target modules. The method compares the output operation properties with the expecting operation properties.
    Type: Application
    Filed: December 27, 2002
    Publication date: July 3, 2003
    Inventors: Yoshiki Matsuoka, Takehiko Tsuchiya, Takeo Nishide, Kazunari Horikawa, Eiichi Yano
  • Semiconductor integrated circuit device and wiring arranging method thereof
    Publication number: 20020117757
    Abstract: Even where an I/O cell requiring good characteristics is alloted to an I/O slot corresponding to the uppermost standard pattern wiring, a pad can be connected to the I/O slot by forming rewiring in the chip outermost peripheral area.
    Type: Application
    Filed: February 25, 2002
    Publication date: August 29, 2002
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shinsuke Sakamoto, Yasuo Inbe, Masakazu Yaginuma, Kazunari Horikawa, Toshikazu Sei