Abstract: Example embodiments provide a semiconductor memory device and a method of verifying the same. The semiconductor memory device may include: a memory including a plurality of memory cells; a verifier determining a program state of the memory cell in the memory; and/or an address/program controller controlling the memory and the verifier. Example embodiments include making the memory start a suspend operation during an operation of the memory cell, and/or starting a verify operation when the suspend operation terminates. The address/program controller may start the operation on the memory cell if it is determined that a repeat operation is necessary, and may start the program operation on the next memory cell if it is determined that a repeat operation is unnecessary. The memory operation mode may be one in which a verify operation is not performed before programming.

Abstract: A nonvolatile semiconductor memory device has a high read output and is not affected by a noise of adjacent bit lines. The memory device is capable of performing high speed read operations. Each bit of a memory as formed by a plurality of memory cells. The memory cells each have the same structure as the structure of a memory cell of the main memory. During a read operation, the bit line is selected and proximate bit lines proximate to the selected bit line are not selected. The nonvolatile semiconductor memory device is formed together with the main memory on one chip by the same process.

Abstract: Example embodiments provide a semiconductor memory device and a method of verifying the same. The semiconductor memory device may include: a memory including a plurality of memory cells; a verifier determining a program state of the memory cell in the memory; and/or an address/program controller controlling the memory and the verifier. Example embodiments include making the memory start a suspend operation during an operation of the memory cell, and/or starting a verify operation when the suspend operation terminates. The address/program controller may start the operation on the memory cell if it is determined that a repeat operation is necessary, and may start the program operation on the next memory cell if it is determined that a repeat operation is unnecessary. The memory operation mode may be one in which a verify operation is not performed before programming.

Abstract: The semiconductor device includes a memory cell array that includes memory cells for storing data and is managed on a sector basis, a memory that stores the information determining the activation status, a latch circuit that latches the activation information according to the information stored in the memory, and a circuit that latches the activation information according to the information stored in the memory in the latch circuit. The activation information according to the memory state of the memory is latched at the time of inputting a given command after activation, and it is thus possible to read the information stored in the memory and set the information in the latch circuit certainly.

Abstract: A nonvolatile semiconductor memory device has a high read output and is not affected by a noise of adjacent bit lines. The memory device is capable of performing high speed read operations. Each bit of a memory as formed by a plurality of memory cells. The memory cells each have the same structure as the structure of a memory cell of the main memory. During a read operation, the bit line is selected and proximate bit lines proximate to the selected bit line are not selected. The nonvolatile semiconductor memory device is formed together with the main memory on one chip by the same process.

Abstract: A semiconductor device includes a first memory cell array that includes memory cells for storing data and is managed on a sector basis, a second memory cell array including memory cells storing sector protection information on the sector basis, and a control circuit checking the sector protection information stored in the second memory cell array whenever the sector to be programmed or erased is selected. Thus, the sector protection information in all the sectors does not have to be latched at the time of power on. The latch circuit equal in number to the sector does not have to be provided. It is thus possible to reduce the number of the circuits drastically and the chip area can be reduced.

Abstract: The semiconductor device of the present invention includes at least one dummy cell of a programmed state proximately located to an edge of a reference cell array. Thus, the leak current does not flow when a data of the cell on the edge of the reference cell array is read out. The memory cell located around the center of the reference cell array has neighboring cells of the programmed state, and the leak current can be prevented when the data is read out from all the reference cells. Thus, the reference current can be supplied stably.

Abstract: The semiconductor device of the present invention includes at least one dummy cell of a programmed state proximately located to an edge of a reference cell array. Thus, the leak current does not flow when a data of the cell on the edge of the reference cell array is read out. The memory cell located around the center of the reference cell array has neighboring cells of the programmed state, and the leak current can be prevented when the data is read out from all the reference cells. Thus, the reference current can be supplied stably.

Abstract: A semiconductor device includes a first memory cell array that includes memory cells for storing data and is managed on a sector basis, a second memory cell array including memory cells storing sector protection information on the sector basis, and a control circuit checking the sector protection information stored in the second memory cell array whenever the sector to be programmed or erased is selected. Thus, the sector protection information in all the sectors does not have to be latched at the time of power on. The latch circuit equal in number to the sector does not have to be provided. It is thus possible to reduce the number of the circuits drastically and the chip area can be reduced.

Abstract: The semiconductor device includes a memory cell array that includes memory cells for storing data and is managed on a sector basis, a memory that stores the information determining the activation status, a latch circuit that latches the activation information according to the information stored in the memory, and a circuit that latches the activation information according to the information stored in the memory in the latch circuit. The activation information according to the memory state of the memory is latched at the time of inputting a given command after activation, and it is thus possible to read the information stored in the memory and set the information in the latch circuit certainly.

Abstract: A semiconductor memory that prevents a decrease in margin at read time. A bit line in a floating state between a drain in a memory cell to be read and a charged bit line is charged for a certain period of time.

Abstract: A semiconductor memory that prevents a decrease in margin at read time. A bit line in a floating state between a drain in a memory cell to be read and a charged bit line is charged for a certain period of time.

Abstract: The input/output nodes of memory cells connected in series are connected to bit lines. Two of the bit lines positioned on the outsides of four successive memory cells constitute each of a plurality of bit line pairs. The bit line pairs are connected to four data lines, respectively, via switches connected to the respective bit lines. A switching control circuit turns on adjacent five of the switches. A switching circuit connects the data lines connected to the input/output nodes by the turning-on of the switches to a supply node of a first voltage, a supply node of a second voltage, and first and second sense amplifiers, respectively. Thereby, data is read from two of the memory cells simultaneously. Thus, it is possible to read data from the two memory cells simultaneously by using the simple switching control circuit without increasing the chip size.

Abstract: The input/output nodes of memory cells connected in series are connected to bit lines. Two of the bit lines positioned on the outsides of four successive memory cells constitute each of a plurality of bit line pairs. The bit line pairs are connected to four data lines, respectively, via switches connected to the respective bit lines. A switching control circuit turns on adjacent five of the switches. A switching circuit connects the data lines connected to the input/output nodes by the turning-on of the switches to a supply node of a first voltage, a supply node of a second voltage, and first and second sense amplifiers, respectively. Thereby, data is read from two of the memory cells simultaneously. Thus, it is possible to read data from the two memory cells simultaneously by using the simple switching control circuit without increasing the chip size.